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llvm-svn: 212973
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We don't have a style guide for diagnostic messages, but convention strongly
favours the forms:
'attribute is not supported', 'unsupported attribute'
We generally avoid:
'attribute is unsupported', 'non-supported attribute'
llvm-svn: 212972
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llvm-svn: 212971
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relevant. Fixes PR18304. Patch by David Wiberg!
llvm-svn: 212970
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llvm-svn: 212969
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(r212805)
llvm-svn: 212968
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The 'select true, %arg, undef' instruction can be used for both aggregate and
non-aggregate arguments.
llvm-svn: 212967
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llvm-svn: 212966
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This reverts commit r212957. It broke the self-host on code like this
from LLVM's option library:
for (auto Arg: filtered(Id0, Id1, Id2))
llvm-svn: 212965
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Use -Winvalid-command-line-argument here to align with existing gcc opt
diagnostics. Meanwhile -Wunused-command-line-argument is for flags that we
support but were, say, fed into the wrong invocation.
Also tweak wording to make sense with -Werror.
llvm-svn: 212964
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llvm-svn: 212963
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llvm-svn: 212962
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llvm-svn: 212961
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llvm-svn: 212960
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same DLL
This is a test case for r212815.
llvm-svn: 212959
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The cmake files for libc++abi and the unwinder weren't linking against
libpthread or an unwind library. If the tests were linked with
-Wl,--as-needed, these libraries wouldn't be linked, causing them to
fail.
Patch contributed by İsmail Dönmez.
llvm-svn: 212958
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Recognize additional cases, when '::' is mistyped as ':'.
This is a fix to RP18587 - colons have too much protection in member-declarations.
Differential Revision: http://reviews.llvm.org/D3653
llvm-svn: 212957
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We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was
due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a
32-bit target. They were added at different times and would result in the
border condition being mishandled.
This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic
operations on x86 at the cost of restoring a long-standing bug in the codegen.
We emit a cmpxchg8b on all x86 targets even where the CPU does not support this
instruction (pre-Pentium CPUs). Although this bug should be fixed, this was
present prior to SVN r212119 and this change, so this is not really introducing
a regression.
llvm-svn: 212956
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Found during windows unwinding work. This header is indirectly included through
a chain leading through Support/Win64EH.h. Explicitly include the header. NFC.
llvm-svn: 212955
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An array showing up in an inline assembly input is accepted in ICC and
GCC 4.8
This fixes PR20201.
Differential Revision: http://reviews.llvm.org/D4382
llvm-svn: 212954
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The size of the uninitialized sections, like BSS, can exceed the size of
the object file.
Do not attempt to grab the contents of such sections.
llvm-svn: 212953
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llvm-svn: 212952
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llvm-svn: 212951
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llvm-svn: 212950
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llvm-svn: 212949
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We construct a temporary "atomicrmw xchg" instruction when lowering atomic
stores for widths that aren't supported natively. This isn't on the top-level
worklist though, so it won't be removed automatically and we have to do it
ourselves once that itself has been lowered.
Thanks Saleem for pointing this out!
llvm-svn: 212948
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This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64,
which generates hint 0x0, the alias of NOP instruction.
This intrinsic is necessary to implement ACLE __nop intrinsic.
Differential Revision: http://reviews.llvm.org/D4495
llvm-svn: 212947
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.data, .reginfo, .MIPS.options, and .MIPS.abiflags
The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.
llvm-svn: 212946
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.data, .reginfo, .MIPS.options, and .MIPS.abiflags
This commit causes multiple lld tests to fail. Reverting while I investigate the issue.
llvm-svn: 212945
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llvm-svn: 212944
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This is a follow-up to r212807
llvm-svn: 212943
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This looks for swapped arguments by looking at implicit conversions of arguments
void Foo(int, double);
Foo(1.0, 3); // Most likely a bug
llvm-svn: 212942
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Reviewers: bkramer
Reviewed By: bkramer
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D4494
llvm-svn: 212941
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Freestanding overloads are represented as FunctionDecls in the AST, make
the matcher also match them.
Differential Revision: http://reviews.llvm.org/D4493
llvm-svn: 212940
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.reginfo, .MIPS.options, and .MIPS.abiflags
Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.
Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.
Differential Revision: http://reviews.llvm.org/D4487
llvm-svn: 212939
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mtc1/mfc1.
Summary:
This is because the FP64A the hardware will redirect 32-bit reads/writes
from/to odd-numbered registers to the upper 32-bits of the corresponding
even register. In effect, simulating FR=0 mode when FR=0 mode is not
available.
Unfortunately, we have to make the decision to avoid mfc1/mtc1 before
register allocation so we currently do this for even registers too.
FPXX has a similar requirement on 32-bit architectures that lack
mfhc1/mthc1 so this patch also handles the affected moves from the FPU for
FPXX too. Moves to the FPU were supported by an earlier commit.
Differential Revision: http://reviews.llvm.org/D4484
llvm-svn: 212938
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llvm-svn: 212937
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FP64 moves
Summary:
This is similar to r210771 which did the same thing for MTHC1.
Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.
Differential Revision: http://reviews.llvm.org/D4483
llvm-svn: 212936
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Before:
fn(a)(b)+1;
After:
fn(a)(b) + 1;
llvm-svn: 212935
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PRIVATE.
For example, c-index-test.exe requires just libclang.dll (its import library).
When libraries in libclang were not PRIVATE but PUBLIC, c-index-test required libraries transitive by libclang.
Note, on mingw with BUILD_SHARED_LIBS, library dependencies would become more strict.
In principle, required libraries should be "required in its source file".
This will help to detect missing dependencies.
llvm-svn: 212934
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Sufficiently twisted use of TableGen lets us write patterns directly for f16
(as an i16 promoted to i32) -> f32 conversion.
llvm-svn: 212933
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'.module oddspreg' is used
Differential Revision: http://reviews.llvm.org/D4486
llvm-svn: 212932
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Summary:
Add __ILP32__ and _ILP32 macro for corresponding platforms.
Cover x86_64-*-*-gnux32 with test.
Test Plan: test added
Reviewers: chandlerc, atanasyan
Subscribers: cfe-commits, dschuff, zinovy.nis
Differential Revision: http://reviews.llvm.org/D4473
llvm-svn: 212931
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enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)
This prevents the upper 32-bits of a double precision value from being moved to
the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure
that the code generated executes correctly regardless of the current FPU mode.
MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue
to use dmtc1.
Differential Revision: http://reviews.llvm.org/D4465
llvm-svn: 212930
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This was done by calling __cxa_demangle directly, which is bad
when c++abi library is instrumented. The following line always
contains the demangled name (when running with a symbolizer) anyway.
llvm-svn: 212929
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llvm-svn: 212928
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llvm-svn: 212927
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Fixed in r212872.
llvm-svn: 212926
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We move back to a simple approach where the liveout is the last must-write
statement for a data-location plus all may-write statements. The previous
approach did not work out. We would have to consider per-data-access
dependences, instead of per-statement dependences to correct it. As this adds
complexity and it seems we would not gain anything over the simpler approach
that we implement in this commit, I moved us back to the old approach of
computing the liveout, but enhanced it to also add may-write accesses.
We also fix the test case and explain why we can not perform dead code
elimination in this case.
llvm-svn: 212925
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Summary:
This patch implements a subset of possible replacements of C-style
casts with const_cast/static_cast/reinterpret_cast. This should cover a large
portion of cases in real code. Handling of a few more cases may be implemented
eventually.
Reviewers: sbenza, djasper
Reviewed By: djasper
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D4478
llvm-svn: 212924
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