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* [Tests] Add a tricky LFTR case for documentation purposesPhilip Reames2019-06-201-0/+64
| | | | | | Thought of this case while working on something else. We appear to get it right in all of the variations I tried, but that's by accident. So, add a test which would catch the potential bug. llvm-svn: 363953
* Store a pointer to the return value in a static alloca and let the debugger ↵Amy Huang2019-06-2014-23/+306
| | | | | | | | | | | | | | use that as the variable address for NRVO variables. Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D63361 llvm-svn: 363952
* [InstCombine] cttz(-x) -> cttz(x)David Bolvansky2019-06-202-16/+32
| | | | | | | | | | | | | | | | Summary: Signedness does not change number of trailing zeros. Reviewers: spatel, lebedev.ri, nikic Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63534 llvm-svn: 363951
* AMDGPU: Eliminate test usage of legacy FP elim attributesMatt Arsenault2019-06-202-3/+3
| | | | llvm-svn: 363950
* AMDGPU: Fix ignoring DisableFramePointerElim in leaf functionsMatt Arsenault2019-06-202-15/+48
| | | | | | | | The attribute can specify elimination for leaf or non-leaf, so it should always be considered. I copied this bug from AArch64, which probably should also be fixed. llvm-svn: 363949
* [clang-ifs] Clang Interface Stubs, first version (second landing attempt).Puyan Lotfi2019-06-2023-0/+956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change reverts r363649; effectively re-landing r363626. At this point clang::Index::CodegenNameGeneratorImpl has been refactored into clang::AST::ASTNameGenerator. This makes it so that the previous circular link dependency no longer exists, fixing the previous share lib (-DBUILD_SHARED_LIBS=ON) build issue which was the reason for r363649. Clang interface stubs (previously referred to as clang-ifsos) is a new frontend action in clang that allows the generation of stub files that contain mangled name info that can be used to produce a stub library. These stub libraries can be useful for breaking up build dependencies and controlling access to a library's internal symbols. Generation of these stubs can be invoked by: clang -fvisibility=<visibility> -emit-interface-stubs \ -interface-stub-version=<interface format> Notice that -fvisibility (along with use of visibility attributes) can be used to control what symbols get generated. Currently the interface format is experimental but there are a wide range of possibilities here. Currently clang-ifs produces .ifs files that can be thought of as analogous to object (.o) files, but just for the mangled symbol info. In a subsequent patch I intend to add support for merging the .ifs files into one .ifs/.ifso file that can be the input to something like llvm-elfabi to produce something like a .so file or .dll (but without any of the code, just symbols). Differential Revision: https://reviews.llvm.org/D60974 llvm-svn: 363948
* [CodeGen] Fix formatting and comments (NFC)Evandro Menezes2019-06-205-93/+95
| | | | llvm-svn: 363947
* [AMDGPU] gfx10 tests. NFC.Stanislav Mekhanoshin2019-06-2021-191/+235367
| | | | llvm-svn: 363946
* [InstCombine] add commuted variants for power-of-2 checks; NFCSanjay Patel2019-06-201-0/+47
| | | | llvm-svn: 363945
* [Sema] Diagnose addr space mismatch while constructing objectsAnastasia Stulova2019-06-208-4/+92
| | | | | | | | | | | | | | If we construct an object in some arbitrary non-default addr space it should fail unless either: - There is an implicit conversion from the address space to default /generic address space. - There is a matching ctor qualified with an address space that is either exactly matching or convertible to the address space of an object. Differential Revision: https://reviews.llvm.org/D62156 llvm-svn: 363944
* Dump more information about expressions involving temporaries when dumping ↵Aaron Ballman2019-06-205-2/+516
| | | | | | the AST to JSON. llvm-svn: 363943
* [pstl] Mark pstl tests as unsupported before C++17Louis Dionne2019-06-2059-2/+118
| | | | | | This is required to run the tests in lit with libc++'s tests. llvm-svn: 363942
* AMDGPU: Treat undef as an inline immediateMatt Arsenault2019-06-203-9/+21
| | | | | | | This should only matter in vectors with an undef component, since a full undef vector would have been folded out. llvm-svn: 363941
* AMDGPU: Make test functions hiddenMatt Arsenault2019-06-201-23/+23
| | | | | | Reduces amount of code in the function from eliminating the GOT load. llvm-svn: 363940
* AIX system headers need stdint.h and inttypes.h to be re-enterableXing Xue2019-06-205-0/+288
| | | | | | | | | | | | | | | | | Summary: AIX system headers need stdint.h and inttypes.h to be re-enterable when macro _STD_TYPES_T is defined so that limit macro definitions such as UINT32_MAX can be found. This patch attempts to allow that on AIX. Reviewers: hubert.reinterpretcast, jasonliu, mclow.lists, EricWF Reviewed by: hubert.reinterpretcast, mclow.lists Subscribers: jfb, jsji, christof, cfe-commits, libcxx-commits, llvm-commits Tags: #LLVM, #clang, #libc++ Differential Revision: https://reviews.llvm.org/D59253 llvm-svn: 363939
* [InstCombine] add tests for checking power-of-2; NFCSanjay Patel2019-06-201-0/+138
| | | | llvm-svn: 363938
* [NFC][SLP] Pre-commit unary FNeg test to X86/phi3.llCameron McInally2019-06-201-0/+41
| | | | llvm-svn: 363937
* [ARM] Add a batch of MVE integer instructions.Simon Tatham2019-06-205-1/+1127
| | | | | | | | | | | | | | | | This includes integer arithmetic of various kinds (add/sub/multiply, saturating and not), and the immediate forms of VMOV and VMVN that load an immediate into all lanes of a vector. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62674 llvm-svn: 363936
* Removing a helper function that was trivial to inline into its only use; NFC.Aaron Ballman2019-06-202-11/+3
| | | | llvm-svn: 363935
* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-2032-60/+1933
| | | | | | Differential Revision: https://reviews.llvm.org/D63204 llvm-svn: 363934
* [unittests] Use object library if cmake supports itTatyana Krasnukha2019-06-201-2/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D63544 llvm-svn: 363933
* Add test cases for explicit casts when dumping the AST to JSON; NFC.Aaron Ballman2019-06-202-0/+2213
| | | | llvm-svn: 363932
* Virtualize TargetInstrInfo::getRegClass()Stanislav Mekhanoshin2019-06-201-0/+1
| | | | | | | | | | | | | AMDGPU target needs to override getRegClass() used during instruction selection. We now may have either 32 or 64 bit conditional registers used in the same instructions. For that purpose special SReg_1 register class is created which is dynamically resolved to either SReg_64 or SGPR_32 depending on the subtarget attributes. Differential Revision: https://reviews.llvm.org/D63205 llvm-svn: 363931
* [yaml2obj] - Convert `ELFState<ELFT>::addSymbols` method to `toELFSymbols` ↵George Rimar2019-06-201-47/+44
| | | | | | | | | | | | | | helper. NFCI. ELFState<ELFT>::addSymbols method looks a bit strange. User code have to create the destination symbols vector outside, add a null symbol and then pass it to addSymbols when it seems the more natural logic is to isolate all work with symbols inside some function, build the list right there and return it. Differential revision: https://reviews.llvm.org/D63493 llvm-svn: 363930
* [DAGCombiner] Support (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), ↵Simon Pilgrim2019-06-202-44/+32
| | | | | | | | C)) non-uniform folds. Use matchBinaryPredicate instead of isConstOrConstSplat to let us handle non-uniform shift cases. llvm-svn: 363929
* [ELF][ARM][AARCH64][MIPS][PPC] Simplify the logic to create R_*_RELATIVE for ↵Fangrui Song2019-06-2013-92/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | absolute relocation types in writable sections Summary: Our rule to create R_*_RELATIVE for absolute relocation types were loose. D63121 made it stricter but it failed to create R_*_RELATIVE for R_ARM_TARGET1 and R_PPC64_TOC. rLLD363236 worked around that by reinstating the original behavior for ARM and PPC64. This patch is an attempt to simplify the logic. Note, in ld.bfd, R_ARM_TARGET2 --target2=abs also creates R_ARM_RELATIVE. This seems a very uncommon scenario (moreover, --target2=got-rel is the default), so I do not implement any logic related to it. Also, delete R_AARCH64_ABS32 from AArch64::getDynRel. We don't have working ILP32 support yet. Allowing it would create an incorrect R_AARCH64_RELATIVE. For MIPS, the (if SymbolRel, then RelativeRel) code is to keep its behavior unchanged. Note, in ppc64-abs64-dyn.s, R_PPC64_TOC gets an incorrect addend because computeAddend() doesn't compute the correct address. We seem to have the wrong behavior for a long time. The important thing seems that a dynamic relocation R_PPC64_TOC should not be created as the dynamic loader will error R_PPC64_TOC is not supported. Reviewers: atanasyan, grimar, peter.smith, ruiu, sfertile, espindola Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D63383 llvm-svn: 363928
* [ELF][ARM] Merge handleARMTlsRelocation() into handleTlsRelocation()Fangrui Song2019-06-202-68/+38
| | | | | | | | | | | | | | | | | | | | | | | ARM and RISC-V do not support TLS relaxations. However, for General Dynamic and Local Dynamic models, if we are producing an executable and the symbol is non-preemptable, we know it must be defined and the R_ARM_TLS_DTPMOD32/R_RISCV_TLS_DTPMOD{32,64} dynamic relocation can be omitted because it is always 1. This may be necessary for static linking as DTPMOD may not be expected at load time. Merge handleARMTlsRelocation() into handleTlsRelocation(). This requires more logic to R_TLSGD_PC and R_TLSLD_PC. Because we use SymbolicRel to resolve the relocation at link time, R_ARM_TLS_DTPMOD32 can be deleted from relocateOne(). It cannot be used as a static relocation type. As a bonus, the additional logic in R_TLSGD_PC code can be shared by the TLS support for RISC-V (D63220). Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D63333 llvm-svn: 363927
* Dump more information about construct expressions (resolved and unresolved) ↵Aaron Ballman2019-06-204-384/+590
| | | | | | when dumping the AST to JSON. llvm-svn: 363926
* [SLP][X86] Add lookahead reordering tests from D60897Simon Pilgrim2019-06-201-3/+235
| | | | llvm-svn: 363925
* [DAGCombine] Add TODOs for some combines that should support non-uniform vectorsSimon Pilgrim2019-06-201-0/+15
| | | | | | We tend to only test for scalar/scalar consts when really we could support non-uniform vectors using ISD::matchUnaryPredicate/matchBinaryPredicate etc. llvm-svn: 363924
* [lldb] [Process/NetBSD] Remove unnecessary register buffer abstractionMichal Gorny2019-06-204-117/+12
| | | | | | | | | | | | | | | | | Remove most of the abstraction over ptrace() register operations, as it has little value and introduces more code than it saves. Instead, leave a single ptrace() wrapper method and call it directly from ReadRegisterSet() and WriteRegisterSet() with correct PT_* request and buffer. Remove the remaining direct ReadGPR() and WriteGPR() invocations with ReadRegisterSet() and WriteRegisterSet(). Cleanup suggested by Pavel Labath in D63545. Differential Revision: https://reviews.llvm.org/D63594 llvm-svn: 363923
* [X86] LowerAVXExtend - handle ANY_EXTEND_VECTOR_INREG lowering as well.Simon Pilgrim2019-06-201-6/+10
| | | | llvm-svn: 363922
* [DAGCombine] Reduce scope of ShAmtVal variable. NFCI.Simon Pilgrim2019-06-201-2/+1
| | | | | | | | Fixes cppcheck warning. Use the more capable getAPIntVal() instead of getZExtValue() as well since I'm here. llvm-svn: 363921
* Revert "[clang] Fixing windows buildbot after D61552"Gauthier Harnisch2019-06-201-2/+0
| | | | | | | | This reverts commit 5d5d2ca69e2b29b36db1a7dd1993ead7b7d2680f. has already been fixed by c230eea2f349533468e14672eee94c2016476784 llvm-svn: 363920
* [clang] Fixing windows buildbot after D61552Gauthier Harnisch2019-06-201-0/+2
| | | | | | | | | | | | | | | | Summary: original review : https://reviews.llvm.org/D61552 build bot faillure : http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/110 this adds a missing definition of cxxDeductionGuideDecl. surprisingly it was still working on linux with out it. Reviewers: aaron.ballman Differential Revision: https://reviews.llvm.org/D63592 llvm-svn: 363919
* [llvm-nm] Generalize ELF symbol types 'N' and 'n'Fangrui Song2019-06-202-13/+28
| | | | | | | | Reviewed By: grimar, jhenderson Differential Revision: https://reviews.llvm.org/D63588 llvm-svn: 363918
* [clang][ASTMatchers] Add definition for cxxDeductionGuideDecl introduced in ↵Kadir Cetinkaya2019-06-201-0/+2
| | | | | | rL363855 llvm-svn: 363917
* [Testing] Dumping the graph requires assertions be enabledDavid Zarzycki2019-06-201-0/+1
| | | | llvm-svn: 363916
* Fix -Wmismatched-tags introduced in r363910Pavel Labath2019-06-203-4/+1
| | | | | | | | That commit changed DIERef from a struct to a class, but did not update the forward-declarations. This fixes one forward-declaration, and removes other (unused) decls. llvm-svn: 363915
* [NFC] Update documentation for AtomicCmpXchgInstSerge Guelton2019-06-201-2/+4
| | | | | | Fix bz#42325 llvm-svn: 363914
* TargetParserTest.ARMExtensionFeatures run out of memory on 32-bit (PR42316)Sjoerd Meijer2019-06-201-21/+68
| | | | | | | | | | | | | | | Nothing of these tests made much sense. Loops were iterating too much, and I also don't think it was actually testing anything. I think we simply want to check that AEK_SOME_EXT returns "+some_ext". I've given the AArch64 tests the same treatment as they very similarly didn't made any sense either. This fixes PR42316. Differential Revision: https://reviews.llvm.org/D63569 llvm-svn: 363913
* [MIPS GlobalISel] Select integer to floating point conversionsPetar Avramovic2019-06-207-2/+675
| | | | | | | | Select G_SITOFP and G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D63542 llvm-svn: 363912
* [MIPS GlobalISel] Select floating point to integer conversionsPetar Avramovic2019-06-208-2/+709
| | | | | | | | Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
* DWARF: Provide accessors to DIERef fieldsPavel Labath2019-06-209-24/+65
| | | | | | | | | | | | | | | | | | | | | | Summary: Instead of accessing the fields directly, use accessor functions to provide access to the DIERef components. This allows us to decouple the external interface, from the internal representation. The external interface can use llvm::Optional and similar goodies, while the data can still be stored internally in a more compact representation. I also document the purpose of the existing DIERef fields. The main motivation for this change is a need to introduce an additional field to the DIERef class, but I believe the change has its own merit. Reviewers: JDevlieghere, aprantl, clayborg Subscribers: arphaman, lldb-commits Differential Revision: https://reviews.llvm.org/D63400 llvm-svn: 363910
* [X86] Add test cases showing missed opportunities to use the C flag from the ↵Craig Topper2019-06-201-0/+65
| | | | | | BLSI instruction to avoid a TEST instruction llvm-svn: 363909
* [clang][AST] Refactoring ASTNameGenerator to use pimpl pattern (NFC).Puyan Lotfi2019-06-202-155/+171
| | | | | | | | | | | The original pimpl pattern used between CodegenNameGenerator and CodegenNameGeneratorImpl did a good job of hiding DataLayout making it so that users of CodegenNameGenerator did not need to link with llvm core. This is an NFC change to neatly wrap ASTNameGenerator in a pimpl. Differential Revision: https://reviews.llvm.org/D63584 llvm-svn: 363908
* [X86] Remove memory instructions form isUseDefConvertible.Craig Topper2019-06-201-15/+15
| | | | | | | | The caller of this is looking for comparisons of the input to these instructions with 0. But the memory instructions input is an addess not a value input in a register. llvm-svn: 363907
* [X86] Add v64i8/v32i16 to several places in X86CallingConv.td where they ↵Craig Topper2019-06-201-3/+4
| | | | | | seemed obviously missing. llvm-svn: 363906
* [libFuzzer] ensure that DFT and autofocus works for C++ (mangled) functionsKostya Serebryany2019-06-203-6/+13
| | | | llvm-svn: 363905
* AMDGPU: Don't clobber VCC in MUBUF addr64 emulationMatt Arsenault2019-06-202-17/+24
| | | | | | | | | Introducing VCC defs during SIFixSGPRCopies is generally problematic. Avoid it by starting with the VOP3 form with the general condition register. This is the easiest to fix instance, but doesn't solve any specific problems I'm looking at. llvm-svn: 363904
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