summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-01257-1378/+1535
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! Note: I accidentally committed a bogus older version of this patch previously. llvm-svn: 218787
* LTO: Add missing target triple from r218784Duncan P. N. Exon Smith2014-10-011-0/+2
| | | | llvm-svn: 218786
* Add fptrunc to mips fast-selReed Kotler2014-10-012-0/+45
| | | | | | | | | | | | | | | | | | Summary: Implement conversion of 64 to 32 bit floating point numbers (fptrunc) in mips fast-isel Test Plan: fptrunc.ll checked also with 4 internal mips build bot flavors mip32r1/miprs32r2 and at -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: rfuhler Differential Revision: http://reviews.llvm.org/D5553 llvm-svn: 218785
* LTO: Ignore disabled diagnostic remarksDuncan P. N. Exon Smith2014-10-017-14/+91
| | | | | | | | | | | | | | | | | | | | | | | r206400 and r209442 added remarks that are disabled by default. However, if a diagnostic handler is registered, the remarks are sent unfiltered to the handler. This is the right behaviour for clang, since it has its own filters. However, the diagnostic handler exposed in the LTO API receives only the severity and message. It doesn't have the information to filter by pass name. For LTO, disabled remarks should be filtered by the producer. I've changed `LLVMContext::setDiagnosticHandler()` to take a `bool` argument indicating whether to respect the built-in filters. This defaults to `false`, so other consumers don't have a behaviour change, but `LTOCodeGenerator::setDiagnosticHandler()` sets it to `true`. To make this behaviour testable, I added a `-use-diagnostic-handler` command-line option to `llvm-lto`. This fixes PR21108. llvm-svn: 218784
* Add an immovable type to test Optional<T>::emplace more rigorously after ↵David Blaikie2014-10-011-5/+26
| | | | | | r218732. llvm-svn: 218783
* Revert r218778 while investigating buldbot breakage.Adrian Prantl2014-10-01257-1530/+1378
| | | | | | "Move the complex address expression out of DIVariable and into an extra" llvm-svn: 218782
* Reverting r218777 while investigating buildbot breakage.Adrian Prantl2014-10-017-38/+34
| | | | | | "Update CGDebugInfo to the updated API in LLVM." llvm-svn: 218781
* c++ error recovery. Build a valid AST when tryingFariborz Jahanian2014-10-011-1/+3
| | | | | | | | | to recover from parse error parsing the default argument. Patch prevents crash after spewing 100s of errors caused by someone who forgot to compile in c++11 mode. So no test. rdar://18508589 llvm-svn: 218780
* Do not use delegated constructors.Samuel Benzaquen2014-10-011-3/+9
| | | | | | | | Do not use delegated constructors. It is not supported on all platforms yet. Fixes build broken by r218769. llvm-svn: 218779
* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-01257-1378/+1530
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! llvm-svn: 218778
* Update CGDebugInfo to the updated API in LLVM.Adrian Prantl2014-10-017-34/+38
| | | | | | | | | | Complex address expressions are no longer part of DIVariable, but rather an extra argument to the debug intrinsics. http://reviews.llvm.org/D4919 rdar://problem/17994491 llvm-svn: 218777
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-01266-1520/+1521
| | | | | | table llvm-svn: 218776
* C API: Add LLVMCloneModule()Tom Stellard2014-10-012-0/+13
| | | | llvm-svn: 218775
* Adds 'override' to overriding methods. NFC.Fariborz Jahanian2014-10-0111-29/+30
| | | | | | These were uncoveredby my yet undelivered patch. llvm-svn: 218774
* thread state coordinator: replaced shortened type name Func suffix with ↵Todd Fiala2014-10-012-30/+30
| | | | | | | | | | | | Function. ThreadIDFunc => ThreadIDFunction LogFunc => LogIDFunction We try to avoid abbreviations/shortened names. Adjusted function parameter names as well to replace _func with _function. llvm-svn: 218773
* [clang-tidy] Clarify a comment.Alexander Kornienko2014-10-011-1/+2
| | | | | | No functional changes. llvm-svn: 218772
* Revert r216862 due to a performance regressionJingyue Wu2014-10-014-59/+28
| | | | | | Reported by Alexey Volkov in PR21115 llvm-svn: 218771
* Minor tweak to Ed's FreeBSD fix.Todd Fiala2014-10-011-1/+1
| | | | | | | Fall back to including the Linux version if not on __FreeBSD__. Also covers __ANDROID__ case. llvm-svn: 218770
* Refactor Matcher<T> and DynTypedMatcher to reduce overhead of casts.Samuel Benzaquen2014-10-016-215/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change introduces DynMatcherInterface and changes the internal representation of DynTypedMatcher and Matcher<T> to use a generic interface instead. It removes unnecessary indirections and virtual function calls when converting matchers by implicit and dynamic casts. DynTypedMatcher now remembers the stricter type in the chain of casts and checks it before calling into DynMatcherInterface. This change improves our clang-tidy related benchmark by ~14%. Also, it opens the door for more optimizations of this kind that are coming in future changes. As a side effect of removing these template instantiations, it also speeds up compilation of Dynamic/Registry.cpp by ~17% and reduces the number of symbols generated by ~30%. Reviewers: klimek Subscribers: klimek, cfe-commits Differential Revision: http://reviews.llvm.org/D5542 llvm-svn: 218769
* [mips] Rename emit and parse functions for the .cpload assembler directive. NFC.Toma Tabacu2014-10-013-10/+10
| | | | | | | | | | | | | | Summary: It's better if we have a consistent name for .cpload-related functions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5437 llvm-svn: 218768
* R600/SI: Add a generic pseudo EXP instructionTom Stellard2014-10-013-8/+30
| | | | llvm-svn: 218767
* R600/SI: Add generic pseudo MTBUF instructionsTom Stellard2014-10-013-31/+58
| | | | llvm-svn: 218766
* R600/SI: Add generic pseudo SMRD instructionsTom Stellard2014-10-012-14/+39
| | | | llvm-svn: 218765
* [asan] Scale back mmap_limit_mb test.Evgeniy Stepanov2014-10-011-4/+4
| | | | | | | | There is some strange interaction between mmap limit and unlimited stack (ulimit -s unlimited), which results in this test failing when run with "make". llvm-svn: 218764
* [ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5Oliver Stannard2014-10-014-52/+82
| | | | | | | | | | Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763
* Add a bandaid to fix the FreeBSD buildEd Maste2014-10-011-0/+4
| | | | | | | | | | | | r218568 added an explicit #include of the Linux ProcessMonitor.h to POSIXThread.cpp, rather than including just "ProcessMonitor.h" and relying on the build infrastructure for the appropriate paths. For now add #ifdefs in the source to use the FreeBSD or Linux header as appropriate; a cleaner fix (and perhaps some refactoring of the POSIX classes) should still be done later. llvm-svn: 218762
* [sanitizer] Add i686 arch to compiler-rt.Evgeniy Stepanov2014-10-015-7/+14
| | | | | | | | | | This is needed so we can produce -i686- named libraries for x86 Android (which is i686-linux-android). An alternative solution would be keeping the "i386" name internally and tweaking the OUTPUT_NAME of compiler-rt libraries. llvm-svn: 218761
* [clang-tidy] Handle c-style casts from/to enums.Alexander Kornienko2014-10-012-12/+31
| | | | | | | | | | | | | | Summary: Convert c-style casts between integral end enum types to static_cast<>. Reviewers: klimek Reviewed By: klimek Subscribers: curdeius, cfe-commits Differential Revision: http://reviews.llvm.org/D5558 llvm-svn: 218760
* [asan] Tune down mmap_limit_mb test.Evgeniy Stepanov2014-10-011-6/+6
| | | | | | The memory limits were a bit too large for 32-bit Android. llvm-svn: 218759
* [RTC] Use the domain to split alias groups.Johannes Doerfert2014-10-013-0/+149
| | | | | | | | | | | | | | We use a parametric abstraction of the domain to split alias groups if accesses cannot be executed under the same parameter evaluation. The two test cases check that we can remove alias groups if the pointers which might alias are never accessed under the same parameter evaluation and that the minimal/maximal accesses are not global but with regards to the parameter evaluation. Differential Revision: http://reviews.llvm.org/D5436 llvm-svn: 218758
* [RTC] Split alias groups according to read only base addressesJohannes Doerfert2014-10-014-16/+99
| | | | | | | | | | | | If there are multiple read only base addresses in an alias group we can split it into multiple alias groups each with only one read only access. This way we might reduce the number of comparisons significantly as it grows linear in the number of alias groups but exponential in their size. Differential Revision: http://reviews.llvm.org/D5435 llvm-svn: 218757
* [x86] Fix a few more tiny patterns with the new vector shuffle loweringChandler Carruth2014-10-012-5/+213
| | | | | | | | | | | | | | | | | | | that keep cropping up in the regression test suite. This also addresses one of the issues raised on the mailing list with failing to form 'movsd' in as many cases as we realistically should. There will be corresponding patches forthcoming for v4f32 at least. This was a lot of fuss for a relatively small gain, but all the fuss was on my end trying different ways of holding the pieces of the x86 fragment patterns *just right*. Now that it works, the code is reasonably simple. In the new test cases I'm adding here, v2i64 sticks out as just plain horrible. I've not come up with any great ideas here other than that it would be nice to recognize when we're *going* to take a domain crossing hit and cross earlier to get the decent instructions. At least with AVX it is slightly less silly.... llvm-svn: 218756
* [x86] Delete some extraneous logic from the new vector shuffle lowering.Chandler Carruth2014-10-011-7/+0
| | | | | | | | Nothing was relying on this and there are potentially some edge cases that it would not be correct under. Removing it seems better than trying to "fix" it as nothing was relying on it. llvm-svn: 218755
* Adding a test for k5 binariesMatthew Gardiner2014-10-012-0/+1
| | | | llvm-svn: 218754
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-018-70/+44
| | | | | | | | | | | | | | | | | | | | | The A64 instruction set includes a generic register syntax for accessing implementation-defined system registers. The syntax for these registers is: S<op0>_<op1>_<CRn>_<CRm>_<op2> The encoding space permitted for implementation-defined system registers is: op0 op1 CRn CRm op2 11 xxx 1x11 xxxx xxx The full encoding space can now be accessed: op0 op1 CRn CRm op2 xx xxx xxxx xxxx xxx This is useful to anyone needing to write assembly code supporting new system registers before the assembler has learned the official names for them. llvm-svn: 218753
* Revert r218721, r218735.Evgeniy Stepanov2014-10-015-283/+9
| | | | | | | | | | Failing bootstrap on Linux (arm, x86). http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/13139/steps/bootstrap%20clang/logs/stdio http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/470 http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/8518 llvm-svn: 218752
* Add missing natual vector cast.Asiri Rathnayake2014-10-013-0/+67
| | | | | | | | | Summary: The natual vector cast node (similar to bitcast) AArch64ISD::NVCAST was introduced in r217159 and r217138. This patch adds a missing cast from v2f32 to v1i64 which is causing some compilation failures. Also added test cases to cover various modimm types and BUILD_VECTORs with i64 elements. llvm-svn: 218751
* ADTTests/OptionalTest.cpp: Use LLVM_DELETED_FUNCTION.NAKAMURA Takumi2014-10-011-4/+4
| | | | llvm-svn: 218750
* Fix the kalimba arch 4 test, broken when I introduced handlingMatthew Gardiner2014-10-011-1/+1
| | | | | | of kalimba architecture variants. llvm-svn: 218749
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DPOliver Stannard2014-10-016-5/+44
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modeled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218748
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)Oliver Stannard2014-10-0111-18/+75
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
* Disable the ubsan-asan config on Darwin.Alexander Potapenko2014-10-012-2/+4
| | | | | | UBSan doesn't work together with ASan on Darwin yet, see http://llvm.org/bugs/show_bug.cgi?id=21112 llvm-svn: 218746
* [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ↵Daniel Sanders2014-10-016-12/+144
| | | | | | | | Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
* [mips] For indirect calls we don't need $gp to point to .got. Mips linkerSasa Stankovic2014-10-018-19/+47
| | | | | | | | | doesn't generate lazy binding stub for a function whose address is taken in the program. Differential Revision: http://reviews.llvm.org/D5067 llvm-svn: 218744
* [OPENMP] Loop collapsing and codegen for 'omp simd' directive.Alexander Musman2014-10-0115-102/+1615
| | | | | | | | | | | | | This patch implements collapsing of the loops (in particular, in presense of clause 'collapse'). It calculates number of iterations N and expressions nesessary to calculate the nested loops counters values based on new iteration variable (that goes from 0 to N-1) in Sema. It also adds Codegen for 'omp simd', which uses (and tests) this feature. Differential Revision: http://reviews.llvm.org/D5184 llvm-svn: 218743
* test: XFAIL the non-darwin gmlt test on darwinJustin Bogner2014-10-011-0/+3
| | | | | | | r218702 disabled a -gmlt optimization for darwin, but this means the non-darwin test isn't working there anymore. llvm-svn: 218742
* [MCJIT] Turn the getSymbolAddress free function created in r218626 into a staticLang Hames2014-10-013-7/+13
| | | | | | | | | | | member of RTDyldMemoryManager (and rename to getSymbolAddressInProcess). The functionality this provides is very specific to RTDyldMemoryManager, so it makes sense to keep it in that class to avoid accidental re-use. No functional change. llvm-svn: 218741
* Improve -Wuninitialized warnings for fields that are record types.Richard Trieu2014-10-012-31/+152
| | | | | | | Get the record handling code from SelfReferenceChecker into UninitializedFieldVisitor as well as copying the testcases. llvm-svn: 218740
* Fix typo in comment from r218733Nick Lewycky2014-10-011-1/+1
| | | | llvm-svn: 218739
* InstrProf: Avoid repeated linear searches in a hot pathJustin Bogner2014-10-015-90/+76
| | | | | | | | | | | | | | | | | | | | | | When generating coverage regions, we were doing a linear search through the existing regions in order to try to merge related ones. Most of the time this would find what it was looking for in a small number of steps and it wasn't a big deal, but in cases with many regions and few mergeable ones this leads to an absurd compile time regression. This changes the coverage mapping logic to do a single sort and then merge as we go, which is a bit simpler and about 100 times faster. I've also added FIXMEs on a couple of behaviours that seem a little suspect, while keeping them behaving as they were - I'll look into these soon. The test changes here are mostly tedious reorganization, because the ordering of regions we output has become slightly (but not completely) more consistent from the almost completely arbitrary ordering we got before. llvm-svn: 218738
OpenPOWER on IntegriCloud