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* [X86] Add missing full stop to comment. NFCI.Simon Pilgrim2018-03-251-1/+1
| | | | llvm-svn: 328456
* [InstSimplify, InstCombine] add/update tests with FP +0.0 vector with undef; NFCSanjay Patel2018-03-258-364/+423
| | | | llvm-svn: 328455
* [X86][SkylakeClient] Fix a set of regular expressions that were checking for ↵Craig Topper2018-03-251-18/+18
| | | | | | | | optionally starting with 'Y' instead of 'V' These bad regexs were introduced by r328435 llvm-svn: 328454
* [X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVecMove than WriteMoveSimon Pilgrim2018-03-251-1/+1
| | | | | | Not that it makes a difference to current cost values, but will when we try to better model GPR-SIMD transfer costs llvm-svn: 328453
* [X86][SkylakeServer] Merge multiple instregex. NFCISimon Pilgrim2018-03-251-7/+7
| | | | llvm-svn: 328452
* [X86] Update cost model for Goldmont. Add fsqrt costs for SilvermontCraig Topper2018-03-254-23/+278
| | | | | | | | | | | | | | Add fdiv costs for Goldmont using table 16-17 of the Intel Optimization Manual. Also add overrides for FSQRT for Goldmont and Silvermont. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44644 llvm-svn: 328451
* [InstCombine] adjust test comments; NFCSanjay Patel2018-03-251-9/+6
| | | | llvm-svn: 328450
* [InstCombine] consolidate casted icmp vector testsSanjay Patel2018-03-251-660/+43
| | | | | | | | We have thorough coverage of predicates and scalar types, so we just need a sampling of vector tests to show that things are working or not with vectors types. llvm-svn: 328449
* [InstCombine] peek through more icmp of FP cast + bitcastSanjay Patel2018-03-252-139/+59
| | | | | | This is an extension of rL328426 as noted in D44367. llvm-svn: 328448
* Remove reference to stale (2009) python version.Yaron Keren2018-03-251-1/+1
| | | | llvm-svn: 328447
* [X86] Add the ability to override memory folding latency to schedules and ↵Simon Pilgrim2018-03-256-29/+35
| | | | | | | | | | add 1uop for memory folds for Intel models The Intel models need an extra 1uop for memory folded instructions, plus a lot of instructions take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up. Differential Revision: https://reviews.llvm.org/D44840 llvm-svn: 328446
* avoid new/delete ellision in construct.pass.cppEric Fiselier2018-03-251-0/+4
| | | | llvm-svn: 328445
* [X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.Craig Topper2018-03-251-79/+79
| | | | llvm-svn: 328444
* [X86] Update a partially stale comment, since SVN r328386. NFC.Martin Storsjo2018-03-241-1/+1
| | | | llvm-svn: 328443
* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* Fix module.modulemap after r328395Eric Fiselier2018-03-241-6/+0
| | | | | | | This patch removes the MachineValueType module since the header was removed in r328395. llvm-svn: 328439
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
* [SchedModel] Record::getName() returns StringRef - avoid std::string ↵Simon Pilgrim2018-03-241-2/+2
| | | | | | creation. NFCI. llvm-svn: 328437
* [SchedModel] Avoid std::string creation for instregex patterns that don't ↵Simon Pilgrim2018-03-241-2/+3
| | | | | | contain regex metas. NFCI. llvm-svn: 328436
* [X86][SkylakeClient] Merge xmm/ymm instructions instregex entries to reduce ↵Simon Pilgrim2018-03-241-1095/+478
| | | | | | regex matches to reduce compile time llvm-svn: 328435
* [X86][Broadwell] Merge xmm/ymm instructions instregex entries to reduce ↵Simon Pilgrim2018-03-241-1119/+489
| | | | | | regex matches to reduce compile time llvm-svn: 328434
* [RISCV] Use init_array instead of ctors for RISCV target, by defaultMandeep Singh Grang2018-03-245-1/+77
| | | | | | | | | | | | | | | | | | | | | Summary: LLVM defaults to the newer .init_array/.fini_array scheme for static constructors rather than the less desirable .ctors/.dtors (the UseCtors flag defaults to false). This wasn't being respected in the RISC-V backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate flag for UseInitArray. This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call InitializeELF(TM.Options.UseInitArray). Reviewers: asb, apazos Reviewed By: asb Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits Differential Revision: https://reviews.llvm.org/D44750 llvm-svn: 328433
* [X86][Haswell] Merge xmm/ymm instructions instregex entries to reduce regex ↵Simon Pilgrim2018-03-241-318/+119
| | | | | | matches to reduce compile time llvm-svn: 328432
* [X86][SandyBridge] Merge xmm/ymm instructions instregex entries to reduce ↵Simon Pilgrim2018-03-241-158/+79
| | | | | | regex matches to reduce compile time llvm-svn: 328431
* [Hexagon] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-03-247-9/+9
| | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44857 llvm-svn: 328430
* [AMDGPU] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-03-241-1/+1
| | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Reviewers: tstellar, RKSimon, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D44856 llvm-svn: 328429
* [llvm-mca] run clang-format on all files.Andrea Di Biagio2018-03-2419-30/+17
| | | | | | This also addresses Simon's review comment in D44839. llvm-svn: 328428
* [llvm-mca] Remove unused field in InstrBuilder. NFCAndrea Di Biagio2018-03-241-1/+0
| | | | llvm-svn: 328427
* [InstCombine] peek through FP casts for sign-bit compares (PR36682)Sanjay Patel2018-03-243-107/+36
| | | | | | | | | | | | This pattern came up in PR36682: https://bugs.llvm.org/show_bug.cgi?id=36682 https://godbolt.org/g/LhuD9A Equality checks are planned as a follow-up enhancement. Differential Revision: https://reviews.llvm.org/D44367 llvm-svn: 328426
* [InstCombine] fix formatting; NFCSanjay Patel2018-03-241-37/+30
| | | | llvm-svn: 328425
* [X86][AES] Ensure we're testing both non-VEX/VEX variants of AES ↵Simon Pilgrim2018-03-241-7/+321
| | | | | | | | instructions on AVX targets Add skylake server tests as well llvm-svn: 328424
* [X86][SSE] Ensure we're testing both non-VEX/VEX variants of SSE ↵Simon Pilgrim2018-03-246-112/+12529
| | | | | | | | instructions on AVX targets And ensure we don't use later instruction sets in SSE schedule tests llvm-svn: 328423
* [InstCombine] add multi-use/vector tests for intrinsic shrinking; NFCSanjay Patel2018-03-241-29/+155
| | | | llvm-svn: 328422
* [X86][AVX1] Ensure we don't use later instruction sets in AVX1 schedule testsSimon Pilgrim2018-03-241-9/+9
| | | | llvm-svn: 328421
* [X86][AVX2] Ensure we don't use later instruction sets in AVX2 schedule testsSimon Pilgrim2018-03-241-9/+13
| | | | llvm-svn: 328420
* [ELF] - Do not ignore discarding of .rela.plt/.rela.dyn, allow doing custom ↵George Rimar2018-03-243-2/+31
| | | | | | | | | | | | | | | | | | | | | | layout for them. Currently when we build input sections list in linker script we ignore all rel[a] sections. That was done to support scripts like .rela.dyn : { *(.rela.data) } for emit relocs. Though as a result following scripts were also silently ignored: /DISCARD/ : { *(.rela.plt) /DISCARD/ : { *(.rela.dyn) and we produced output with this sections. That is not ideal. The solution this patch suggests is simple: do not ignore synthetic rel[a] sections. That way we can enable common discarding logic for them and report a proper error. Differential revision: https://reviews.llvm.org/D41640 llvm-svn: 328419
* [clang-tidy] Enable Python 3 support for add_new_check.pyJonathan Coe2018-03-241-16/+18
| | | | | | | | | | | | | | Summary: In Python 3, filters are lazily evaluated and strings are not bytes. Reviewers: ilya-biryukov Reviewed By: ilya-biryukov Subscribers: xazax.hun, cfe-commits Differential Revision: https://reviews.llvm.org/D44217 llvm-svn: 328418
* [sanitizer] Fix Darwin buildVitaly Buka2018-03-242-3/+7
| | | | llvm-svn: 328417
* [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an ↵Craig Topper2018-03-246-65/+37
| | | | | | | | attribute. This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables. llvm-svn: 328416
* Mmap interceptor providing mprotect supportVitaly Buka2018-03-247-33/+77
| | | | | | | | | | | | | | | | Summary: - Intercepting mprotect calls. - Fixing forgotten flag check. Patch by David CARLIER Reviewers: vitalybuka, vsk Subscribers: delcypher, srhines, kubamracek, llvm-commits, #sanitizers Differential Revision: https://reviews.llvm.org/D44777 llvm-svn: 328415
* [sanitizer] Fix strlcpy and strlcat interceptors on DarwinVitaly Buka2018-03-241-3/+3
| | | | llvm-svn: 328414
* [X86] Use unique_ptr to simplify memory management. NFCCraig Topper2018-03-244-20/+14
| | | | llvm-svn: 328413
* [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF ↵Craig Topper2018-03-241-24/+5
| | | | | | format encodings. NFC llvm-svn: 328412
* [X86] Remove an unnecessary switch around two other switches. NFCCraig Topper2018-03-241-69/+54
| | | | | | The outer switch only had one valid block so didn't provide any value. llvm-svn: 328411
* [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFCCraig Topper2018-03-246-44/+42
| | | | | | The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map. llvm-svn: 328410
* [C++17] Fix class template argument deduction for default constructors ↵Zhihao Yuan2018-03-243-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | without an initializer Summary: As the title says, this makes following code compile: ``` template<typename> struct Foo {}; Foo() -> Foo<void>; Foo f; // ok ``` Thanks Nicolas Lesser for coining the fix. Reviewers: rsmith, lichray Reviewed By: rsmith, lichray Subscribers: lichray, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D38216 llvm-svn: 328409
* Add REQUIRES lines for the targets being checked in this test.Eric Christopher2018-03-241-0/+3
| | | | llvm-svn: 328408
* [HWASan] Fix use-after-free.cc test on x86-64Alex Shlyapnikov2018-03-241-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D44705 llvm-svn: 328407
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