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* [IRCE] Rename variable; NFCSanjoy Das2016-08-021-6/+6
| | | | | | There is nothing "Original" about "OriginalLoopInfo". llvm-svn: 277506
* [IRCE] Preserve DomTree and LCSSASanjoy Das2016-08-023-10/+17
| | | | | | | This changes IRCE to "preserve" LCSSA and DomTree by recomputing them. It still does not preserve LoopSimplify. llvm-svn: 277505
* AMDGPU: Stay in WQM for non-intrinsic storesNicolai Haehnle2016-08-028-54/+107
| | | | | | | | | | | | | | | | | | | | | | | Summary: Two types of stores are possible in pixel shaders: stores to memory that are explicitly requested at the API level, and stores that are an implementation detail of register spilling or lowering of arrays. For the first kind of store, we must ensure that helper pixels have no effect and hence WQM must be disabled. The second kind of store must always be executed, because the written value may be loaded again in a way that is relevant for helper pixels as well -- and there are no externally visible effects anyway. This is a candidate for the 3.9 release branch. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D22675 llvm-svn: 277504
* test commitAlbert Gutowski2016-08-021-1/+1
| | | | llvm-svn: 277503
* [LoopUnroll] Ensure we create prolog loops in simplified form.Michael Zolotukhin2016-08-022-1/+13
| | | | llvm-svn: 277502
* Fix handling of end-of-line preprocessor comments Attempt 2Nirav Dave2016-08-022-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Attempt 2: Retryign after Tsan.mman test fix. Attempt 1: Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277501
* AMDGPU: Track physical registers in SIWholeQuadModeNicolai Haehnle2016-08-023-27/+91
| | | | | | | | | | | | | | | | | | | | Summary: There are cases where uniform branch conditions are computed in VGPRs, and we didn't correctly mark those as WQM. The stray change in basic-branch.ll is because invoking the LiveIntervals analysis leads to the detection of a dead register that would otherwise not be seen at -O0. This is a candidate for the 3.9 branch, as it fixes a possible hang. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22673 llvm-svn: 277500
* [AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC.Ahmed Bougacha2016-08-0210-9/+3
| | | | | | | I forgot the REQUIRES once (see r277486). Let's prevent it from happening again. llvm-svn: 277499
* [AArch64] Remove useless 'import re' from CodeGen lit.local.cfg. NFC.Ahmed Bougacha2016-08-021-2/+0
| | | | llvm-svn: 277498
* [Hexagon] Prefer _io over _rr for 64-bit store with constant offsetKrzysztof Parzyszek2016-08-022-0/+25
| | | | | | | | | Identify patterns where the address is aligned to an 8-byte boundary, but both the base address and the constant offset are both proper multiples of 4. In such cases, extract Base+4 into a separate instruc- tion, and use S2_storerd_io, instead of using S4_storerd_rr. llvm-svn: 277497
* [Hexagon] Remove unused optionKrzysztof Parzyszek2016-08-021-7/+0
| | | | llvm-svn: 277496
* [Concepts] Add TODO and requires-clause placeholder; NFCHubert Tong2016-08-021-1/+3
| | | | llvm-svn: 277495
* [Hexagon] Improvements to address mode checks in TargetLoweringKrzysztof Parzyszek2016-08-022-2/+39
| | | | | | | - Implement getOptimalMemOpType. - Check BaseOffset in isLegalAddressingMode. llvm-svn: 277494
* Revert "[Order Files] Remove dtrace predicate"Chris Bieneman2016-08-021-1/+2
| | | | | | | | This reverts commit r277487. Removing the probe predicate was a red herring. It results in more symbols being placed in the final order file, but they are symbols from outside the clang image. llvm-svn: 277492
* [clang-rename] fix Emacs integration scriptKirill Bobyrev2016-08-021-3/+1
| | | | llvm-svn: 277491
* Update Clang Parser test error message to match new parser errorsNirav Dave2016-08-021-1/+1
| | | | | | Update clang tests in light of r277489. llvm-svn: 277490
* [MC] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-08-023-116/+98
| | | | | | | | | | | | | | | | | Recommitting after fixing overaggressive fastpath return in parsing. Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Associated commit to fix clang test commited shortly. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 277489
* Updated documentationVitaly Buka2016-08-021-1/+2
| | | | | | | | | | Reviewers: kcc, eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22992 llvm-svn: 277488
* [Order Files] Remove dtrace predicateChris Bieneman2016-08-021-2/+1
| | | | | | Having the dtrace predicate setup to only show probes in clang filters out static initializers executed by dyld, which we do want included in the order files. llvm-svn: 277487
* [AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests.Ahmed Bougacha2016-08-022-2/+8
| | | | | | | | I thought the directory had a lit.local.cfg, but it doesn't. I'll add one, but for now, add the REQUIRES line. While there, move the triple into the IR and add a datalayout. llvm-svn: 277486
* MSVC 2013 does not implement C++11 unions properly, so remove the anoymous ↵Daniel Berlin2016-08-021-2/+2
| | | | | | | | union for now, and leave a FIXME. llvm-svn: 277485
* [GlobalISel] Set the Selected MF property.Ahmed Bougacha2016-08-023-14/+23
| | | | | | | None of GlobalISel requires the property, but this lets us use the verifier instead of rolling our own "all instructions selected" check. llvm-svn: 277484
* [GlobalISel] Verify Selected MF property.Ahmed Bougacha2016-08-022-1/+46
| | | | | | | | After instruction selection, there should be no pre-isel generic instructions remaining, nor should generic virtual registers be used. Verify that. llvm-svn: 277483
* [GlobalISel] Add Selected MachineFunction property.Ahmed Bougacha2016-08-026-0/+20
| | | | | | | | | | | | | | | | Selected: the InstructionSelect pass ran and all pre-isel generic instructions have been eliminated; i.e., all instructions are now target-specific or non-pre-isel generic instructions (e.g., COPY). Since only pre-isel generic instructions can have generic virtual register operands, this also means that all generic virtual registers have been constrained to virtual registers (assigned to register classes) and that all sizes attached to them have been eliminated. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277482
* Rewrite the use optimizer to be less memory intensive and 50% faster.Daniel Berlin2016-08-022-33/+321
| | | | | | | | | | | | | | | | | | | | | | | | Fixes PR28670 Summary: Rewrite the use optimizer to be less memory intensive and 50% faster. Fixes PR28670 The new use optimizer works like a standard SSA renaming pass, storing all possible versions a MemorySSA use could get in a stack, and just tracking indexes into the stack. This uses much less memory than caching N^2 alias query results. It's also a lot faster. The current version defers phi node walking to the normal walker. Reviewers: george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23032 llvm-svn: 277480
* [LVI] NFC. Sink a condition type check from the caller down to ↵Artur Pilipenko2016-08-021-31/+33
| | | | | | | | getValueFromCondition This is a preparatory refactoring to support conditions other than ICmpInst. llvm-svn: 277479
* [asan] Remove NtWaitForWorkViaWorkerFactory interceptorReid Kleckner2016-08-024-48/+0
| | | | | | | | | | | | | | | | Summary: On Windows 10, this gets called after TLS has been torn down from NTDLL, and we crash attempting to return fake_tsd. This interceptor isn't needed after r242948 anyway, so let's remove it. The ASan runtime can now tolerate unregistered threads calling __asan_handle_no_return. Reviewers: vitalybuka, etienneb Subscribers: kubabrecka, llvm-commits Differential Revision: https://reviews.llvm.org/D23044 llvm-svn: 277478
* [GlobalISel] Set and require RegBankSelected MF property.Ahmed Bougacha2016-08-024-1/+38
| | | | | | | | The InstructionSelect pass assumes that RegBankSelect ran; set the property on all tests (thereby verifying the test inputs) and require it in the pass. llvm-svn: 277477
* [GlobalISel] Verify RegBankSelected MF property.Ahmed Bougacha2016-08-022-1/+38
| | | | | | | RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
* [GlobalISel] Add RegBankSelected MachineFunction property.Ahmed Bougacha2016-08-026-0/+16
| | | | | | | | | | RegBankSelected: the RegBankSelect pass ran and all generic virtual registers have been assigned to a register bank. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277475
* [LV] Generate both scalar and vector integer induction variablesMatthew Simpson2016-08-023-115/+248
| | | | | | | | | | | | | | | | This patch enables the vectorizer to generate both scalar and vector versions of an integer induction variable for a given loop. Previously, we only generated a scalar induction variable if we knew all its users were going to be scalar. Otherwise, we generated a vector induction variable. In the case of a loop with both scalar and vector users of the induction variable, we would generate the vector induction variable and extract scalar values from it for the scalar users. With this patch, we now generate both versions of the induction variable when there are both scalar and vector users and select which version to use based on whether the user is scalar or vector. Differential Revision: https://reviews.llvm.org/D22869 llvm-svn: 277474
* [analyzer] Hotfix for buildbot failure due to unspecified triple in r277449Artem Dergachev2016-08-021-1/+1
| | | | | | | | | If a target triple is not specified, the default host triple is used, which is not good for compiling inline assembler code. Patch by Raphael Isemann! llvm-svn: 277473
* [GlobalISel] Set, require, and verify Legalized MF property.Ahmed Bougacha2016-08-028-2/+90
| | | | | | | | | | | | | RegBankSelect and InstructionSelect run after the legalizer and require a Legalized function: check that all instructions are legal. Note that this should be in the MachineVerifier, but it can't use the MachineLegalizer as it's currently in the separate GlobalISel library. Note that the RegBankSelect verifier checks have the same layering problem, but we only use inline methods so end up not needing to link against the GlobalISel library. llvm-svn: 277472
* [AArch64][GlobalISel] Mark basic binops/memops as legal.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | | | | We currently use and test these, and select most of them. Mark them as legal even though we don't go through the full ir->asm flow yet. This doesn't currently have standalone tests, but the verifier will soon learn to check that the regbankselect/select tests are legal. llvm-svn: 277471
* [GlobalISel] Add Legalized MachineFunction property.Ahmed Bougacha2016-08-026-0/+53
| | | | | | | | | | | | | Legalized: The MachineLegalizer ran; all pre-isel generic instructions have been legalized, i.e., all instructions are now one of: - generic and always legal (e.g., COPY) - target-specific - legal pre-isel generic instructions. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277470
* [clang-rename] fix Emacs script build failureKirill Bobyrev2016-08-021-2/+3
| | | | | | Clang-rename Emacs integration script sometimes doesn't work correctly. llvm-svn: 277469
* Revert "[MC] Fix handling of end-of-line preprocessor comments"Nirav Dave2016-08-022-44/+0
| | | | | | | | Causes TSan failure on PPC64 This reverts commit r277459. llvm-svn: 277468
* [WebAssembly] Remove a README.txt entry that is now implemented.Dan Gohman2016-08-021-6/+0
| | | | llvm-svn: 277467
* [LVI] NFC. Fix a typo getValueFromFromCondition -> getValueFromConditionArtur Pilipenko2016-08-021-11/+9
| | | | llvm-svn: 277466
* [CodeGen] Generalize MachineFunctionProperties::print comma handling.Ahmed Bougacha2016-08-021-2/+7
| | | | | | | | This is only used for debug prints, but the previous hardcoded ", " caused it to be printed unnecessarily when OnlySet, and is annoying when adding new properties. llvm-svn: 277465
* [GlobalISel] Require isSSA in GISel passes.Ahmed Bougacha2016-08-023-0/+15
| | | | | | | The GISel passes don't make sense on non-SSA functions. All GISel tests already set isSSA. Enforce that. llvm-svn: 277464
* Follow-up for r277458: Update the tsan_mman_test.cc unit test.Kuba Brecka2016-08-021-4/+4
| | | | llvm-svn: 277463
* [tsan] Fix the behavior of OSAtomicTestAndClearKuba Brecka2016-08-022-10/+43
| | | | | | | | The system implementation of OSAtomicTestAndClear returns the original bit, but the TSan interceptor has a bug which always returns zero from the function. This patch fixes this and adds a test. Differential Revision: https://reviews.llvm.org/D23061 llvm-svn: 277461
* [LV] Untangle the concepts of uniform and scalarMatthew Simpson2016-08-022-63/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the logic in collectLoopUniforms and collectValuesToIgnore, untangling the concepts of "uniform" and "scalar". It adds isScalarAfterVectorization along side isUniformAfterVectorization to distinguish the two. Known scalar values include those that are uniform, getelementptr instructions that won't be vectorized, and induction variables and induction variable update instructions whose users are all known to be scalar. This patch includes the following functional changes: - In collectLoopUniforms, we mark uniform the pointer operands of interleaved accesses. Although non-consecutive, these pointers are treated like consecutive pointers during vectorization. - In collectValuesToIgnore, we insert a value into VecValuesToIgnore if it isScalarAfterVectorization rather than isUniformAfterVectorization. This differs from the previous functionaly in that we now add getelementptr instructions that will not be vectorized into VecValuesToIgnore. This patch also removes the ValuesNotWidened set used for induction variable scalarization since, after the above changes, it is now equivalent to isScalarAfterVectorization. Differential Revision: https://reviews.llvm.org/D22867 llvm-svn: 277460
* [MC] Fix handling of end-of-line preprocessor commentsNirav Dave2016-08-022-0/+44
| | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277459
* [tsan] Fix behavior of realloc(nullptr, 0) on DarwinKuba Brecka2016-08-022-11/+27
| | | | | | | | On Darwin, there are some apps that rely on realloc(nullptr, 0) returning a valid pointer. TSan currently returns nullptr in this case, let's fix it to avoid breaking binary compatibility. Differential Revision: https://reviews.llvm.org/D22800 llvm-svn: 277458
* [clang-cl] Fix PCH tests to use x86_64 as targetDiana Picus2016-08-023-7/+7
| | | | | | | | | | | | These tests require x86-registered-target, but they don't force the target as x86 on the command line, which means they will be run and they might fail when building the x86 backend on another platform (such as AArch64). Fixes https://llvm.org/bugs/show_bug.cgi?id=28797 Differential Revision: https://reviews.llvm.org/D23054 llvm-svn: 277457
* Fixing 'Aquire' typo and libcxx build.Ben Craig2016-08-022-2/+2
| | | | llvm-svn: 277456
* Revert rL277454David Callahan2016-08-021-1/+0
| | | | llvm-svn: 277455
* test commitDavid Callahan2016-08-021-0/+1
| | | | llvm-svn: 277454
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