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* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
| | | | | | | Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178024
* R600/SI: improve vector interpolationChristian Konig2013-03-261-0/+20
| | | | | | | Prevent loading M0 multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178023
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-262-14/+8
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-263-1/+9
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178021
* R600/SI: mark most intrinsics as readnone v2Christian Konig2013-03-263-54/+89
| | | | | | | | | They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178020
* R600/SI: replace WQM intrinsicChristian Konig2013-03-265-28/+14
| | | | | | | Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178019
* R600/SI: fix ELSE pseudo op handlingChristian Konig2013-03-261-1/+2
| | | | | | | | | | | Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178018
* Patch by Gordon Keiser!Joe Abbey2013-03-262-1/+3
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* Need one more swap overload for swapping two lvalue vector<bool>::reference's.Howard Hinnant2013-03-262-0/+20
| | | | llvm-svn: 178016
* Fix uninitialized read of CalleeWithThisReturn.Evgeniy Stepanov2013-03-261-1/+1
| | | | | | | | | | CalleeWithThisReturn can be left initialized if HasThisReturn() is false. This change reverses the order of checks in EmitFunctionEpilog such that CalleeWithThisReturn is only examined when it has a meaningful value. Found with MemorySanitizer. llvm-svn: 178015
* [ASan] Change the ABI of __asan_before_dynamic_init function: now it takes ↵Alexey Samsonov2013-03-263-21/+16
| | | | | | pointer to private string with module name. This string serves as a unique module ID in ASan runtime. compiler-rt part llvm-svn: 178014
* [ASan] Change the ABI of __asan_before_dynamic_init function: now it takes ↵Alexey Samsonov2013-03-261-17/+13
| | | | | | pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part llvm-svn: 178013
* [libsanitizer] Fix the Win build.Alexander Potapenko2013-03-261-1/+3
| | | | llvm-svn: 178012
* [tsan] make memcpy_race.cc test immune to memcpy inliningKostya Serebryany2013-03-261-2/+4
| | | | llvm-svn: 178011
* asan/tsan: move strcasecmp() interceptor to sanitizer_commonDmitry Vyukov2013-03-266-42/+54
| | | | llvm-svn: 178010
* asan/tsan: change SANITIZER_GO to more general SANITIZER_SUPPORTS_WEAK_HOOKSDmitry Vyukov2013-03-261-2/+2
| | | | llvm-svn: 178009
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-264-7/+21
| | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. llvm-svn: 178008
* PowerPC: Simplify handling of fixups.Ulrich Weigand2013-03-265-70/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. llvm-svn: 178007
* PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand2013-03-264-101/+50
| | | | | | | | | | | | | | | | | | | | | | | As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. llvm-svn: 178006
* PowerPC: Remove LDrs pattern.Ulrich Weigand2013-03-263-16/+9
| | | | | | | | | | | | | | | | | | | | The LDrs pattern is a duplicate of LD, except that it accepts memory addresses where the displacement is a symbolLo64. An operand type "memrs" is defined for just that purpose. However, this wouldn't be necessary if the default "memrix" operand type were to simply accept 64-bit symbolic addresses directly. The only problem with that is that it uses "symbolLo", which is hardcoded to 32-bit. To fix this, this commit changes "memri" and "memrix" to use new operand types for the memory displacement, which allow iPTR instead of i32. This will also make address parsing easier to implment in the asm parser. No change in generated code. llvm-svn: 178005
* PowerPC: Remove ADDIL patterns.Ulrich Weigand2013-03-264-20/+13
| | | | | | | | | | | | | | The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L, which describe the same instruction, except that they accept a symbolLo[64] operand instead of a s16imm[64] operand. This duplication confuses the asm parser, and it actually not really needed, since symbolLo[64] already accepts immediate operands anyway. So this commit removes the duplicate patterns. No change in generated code. llvm-svn: 178004
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-265-46/+19
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* PowerPC: Simplify BLR pattern.Ulrich Weigand2013-03-263-12/+6
| | | | | | | | | | | | | | | | | The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
* PowerPC: Move some 64-bit branch patterns.Ulrich Weigand2013-03-261-17/+18
| | | | | | | | | | | | In PPCInstr64Bit.td, some branch patterns appear in a different sequence than the corresponding 32-bit patterns in PPCInstrInfo.td. To simplify future changes that affect both files, this commit moves those patterns to rearrange them into a similar sequence. No effect on generated code. llvm-svn: 178001
* [libsanitizer] Unmapping the old cache partially invalidates the memory ↵Alexander Potapenko2013-03-267-20/+23
| | | | | | | | | | layout, so add a flag to skip cache update for cases when that's unacceptable (e.g. lsan). Patch by Sergey Matveev (earthdok@google.com) llvm-svn: 178000
* R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig2013-03-261-2/+4
| | | | | | | | | Use a MapVector on types where the iteration order matters. Otherwise we doesn't always produce a deterministic output. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 177999
* [Sanitizer] Disable atomic_test on Android, where it crashes Clang.Alexey Samsonov2013-03-261-0/+4
| | | | llvm-svn: 177998
* Actually mark ASan-unfriendly test as XFAILAlexey Samsonov2013-03-261-0/+3
| | | | llvm-svn: 177997
* [tsan] add a test for aligned-vs-unaligned race (tsan's false negative)Kostya Serebryany2013-03-261-0/+30
| | | | llvm-svn: 177996
* Add asan/msan to the list of available features in LIT test runner. Mark ↵Alexey Samsonov2013-03-262-0/+7
| | | | | | ASan-unfriendly test as XFAIL. llvm-svn: 177995
* Add asan/msan to the list of available features in LIT test runnerAlexey Samsonov2013-03-262-0/+8
| | | | llvm-svn: 177994
* [asan] print thread number while reporting invalid-free and double-free; add ↵Kostya Serebryany2013-03-264-2/+64
| | | | | | tests; also add a test for use-after-poison llvm-svn: 177993
* Add CMake option LLVM_USE_SANITIZER={Address,Memory,MemoryWithOrigins} to ↵Alexey Samsonov2013-03-262-3/+45
| | | | | | simplify bootstrap of LLVM/Clang under ASan/MSan llvm-svn: 177992
* [ELF][Hexagon] Fixing failing test on Bots, few symbol names are available ↵Shankar Easwaran2013-03-261-40/+3
| | | | | | only in debug builds, dont check the symbol names llvm-svn: 177991
* [ELF] no change in functionality, add functions to symbol table so that they ↵Shankar Easwaran2013-03-261-69/+112
| | | | | | can be overridden by derived classes llvm-svn: 177990
* Manually specify the link dependencies. Turns out that all the work onChandler Carruth2013-03-261-1/+1
| | | | | | | LLVMBuild stuff didn't actually provide a single place for dependencies, it just added a third place. llvm-svn: 177989
* Manually update the dependencies in the Makefiles. It turns out that allChandler Carruth2013-03-269-9/+9
| | | | | | | | | | | that work on the LLVMBuild based dependency specification didn't actually work, we just now maintain dependencies in *3* places instead of 2. Yay. There may still be some missing dependencies, I'm still sifting through the bots and my builds, but this is a step in the right direction. llvm-svn: 177988
* Handle CXXOperatorCallExpr when checking self referrnce during initialization ofRichard Trieu2013-03-262-0/+23
| | | | | | class types. llvm-svn: 177987
* Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.Andrew Trick2013-03-263-0/+68
| | | | | | | | | | | | | | | Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal. Indvars creates a SCEV expression for the loop's back edge taken count, then determines that the comparison is always true and removes it. When loop-unroll asks for the expression, it contains a NULL SCEVUnknkown (as a CallbackVH). forgetMemoizedResults should invalidate the loop back edges expression. llvm-svn: 177986
* The IRReader header is now part of its own library. Update the includeChandler Carruth2013-03-264-1/+4
| | | | | | line and the library dependencies to reflect this. llvm-svn: 177972
* Split out the IRReader header and the utility functions it provides intoChandler Carruth2013-03-2633-137/+205
| | | | | | | | | | | | | | | | | | | | | | | | its own library. These functions are bridging between the bitcode reader and the ll parser which are in different libraries. Previously we didn't have any good library to do this, and instead played fast and loose with a "header only" set of interfaces in the Support library. This really doesn't work well as evidenced by the recent attempt to add timing logic to the these routines. As part of this, make them normal functions rather than weird inline functions, and sink the implementation into the library. Also clean up the header to be nice and minimal. This requires updating lots of build system dependencies to specify that the IRReader library is needed, and several source files to not implicitly rely upon the header file to transitively include all manner of other headers. If you are using IRReader.h, this commit will break you (the header moved) and you'll need to also update your library usage to include 'irreader'. I will commit the corresponding change to Clang momentarily. llvm-svn: 177971
* [ELF][Hexagon] add GOTREL/GOT relocationsShankar Easwaran2013-03-265-4/+291
| | | | llvm-svn: 177970
* [ELF] order rela.dyn/rela.plt properlyShankar Easwaran2013-03-264-2/+41
| | | | llvm-svn: 177969
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-264-24/+70
| | | | | | | | Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 177968
* ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer2013-03-261-0/+57
| | | | | | | | | | This is very much work in progress. Please send me a note if you start to depend on the added abstract read/write resources. They are subject to change until further notice. The old itinerary is still the default. llvm-svn: 177967
* <rdar://problem/13502196>Greg Clayton2013-03-261-1/+12
| | | | | | We have the tag when figuring out the fully qualified name, append a suitable name for other types of tags when no name is available. llvm-svn: 177966
* <rdar://problem/13502196> Greg Clayton2013-03-262-2/+14
| | | | | | Functions in "(anonymous namespace)" was causing LLDB to crash when trying to complete a type and it would also cause functions arguments to appear in wrong place in frame display when showing function arguments. llvm-svn: 177965
* Make the stepping perf test case actually work.Jim Ingham2013-03-263-39/+308
| | | | llvm-svn: 177964
* Add missing file to cmake build.Nick Lewycky2013-03-261-0/+1
| | | | llvm-svn: 177963
* Add a new watchdog timer interface. The interface does not permit handling ↵Nick Lewycky2013-03-266-1/+124
| | | | | | | | | timeouts, so it's only really useful if you're going to crash anyways. Use it in the pretty stack trace printer to kill the compiler if we hang while printing the stack trace. llvm-svn: 177962
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