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* Re-submitting changes in D51550 because it failed to patch.Christy Lee2018-09-245-38/+75
| | | | | | | | | | | | Reviewers: javed.absar, trentxintong, courbet Reviewed By: trentxintong Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52433 llvm-svn: 342919
* [InstCombine] add bitcast+extelt helper function; NFCSanjay Patel2018-09-241-14/+26
| | | | | | | | We can handle patterns where the elements have different sizes, so refactoring ahead of trying to add another blob within these clauses. llvm-svn: 342918
* [compiler-rt] [builtins] Add logb/logbf/logbl methods to compiler-rt to ↵Jordan Rupprecht2018-09-249-10/+282
| | | | | | | | | | | | | | | | | | | | | | | avoid libm dependencies when possible. Summary: The complex division builtins (div?c3) use logb methods from libm to scale numbers during division and avoid rounding issues. However, these come from libm, meaning anyone that uses --rtlib=compiler-rt also has to include -lm. Implement logb* methods for standard ieee 754 floats so we can avoid -lm on those platforms, falling back to the old behavior (using either logb() or `__builtin_logb()`) when not supported. These new methods are defined internally as `__compiler_rt_logb` so as not to conflict with the libm definitions in any way. This fixes just the libm methods mentioned in PR32279 and PR28652. libc is still required, although that seems to not be an issue. Note: this is proposed as an alternative to just adding -lm: D49330. Reviewers: efriedma, compnerd, scanon, echristo Reviewed By: echristo Subscribers: jsji, echristo, nemanjai, dberris, mgorny, kbarton, delcypher, llvm-commits, #sanitizers Differential Revision: https://reviews.llvm.org/D49514 llvm-svn: 342917
* [X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim2018-09-247-97/+43
| | | | | | The uops are slightly different to the register variant, so requires a +1uop tweak llvm-svn: 342916
* [lldb-mi] Fix hanging of target-select-so-path.testAlexander Polyakov2018-09-241-13/+21
| | | | | | | | | | | | | | | | | | | | | | | Summary: The target-select-so-path test might hang on some platforms. The reason of that behavior was in incorrect usage of Filecheck and lldb-mi processes. Instead of redirecting lldb-mi's output to Filecheck, we should run lldb-mi session, finish the session, collect its output and then pass it to Filecheck. Also, this patch adds a timer to the test to prevent it from hanging in the future. Reviewers: tatyana-krasnukha, aprantl, teemperor Reviewed By: tatyana-krasnukha, teemperor Subscribers: apolyakov, aprantl, teemperor, ki.stfu, abidh, lldb-commits Differential Revision: https://reviews.llvm.org/D52139 llvm-svn: 342915
* [X86] Infer 64bit feature support from the CPUID results in getHostCPUFeatures.Craig Topper2018-09-241-0/+2
| | | | | | After r341022, we more strictly check the 64bit feature in X86Subtargets constructor when a 64-bit triple is used. If we don't infer this feature for autodetected CPUs we might incorrectly report an error if the CPU name wasn't autodetected to a CPU that supports 64-bit. llvm-svn: 342914
* [profile] Revert commit https://reviews.llvm.org/rL342718Calixte Denizet2018-09-2416-19/+20
| | | | llvm-svn: 342913
* [CodeGen] Revert commit https://reviews.llvm.org/rL342717Calixte Denizet2018-09-2410-43/+32
| | | | llvm-svn: 342912
* [Power9] [CLANG] Add __float128 exponent GET and SET builtinsStefan Pintilie2018-09-242-0/+14
| | | | | | | | | | | | | Added __builtin_vsx_scalar_extract_expq __builtin_vsx_scalar_insert_exp_qp Builtins should behave the same way as in GCC. Differential Revision: https://reviews.llvm.org/D48184 llvm-svn: 342911
* [Power9] [LLVM] Add __float128 exponent GET and SET builtinsStefan Pintilie2018-09-243-0/+49
| | | | | | | | | | | | | Added __builtin_vsx_scalar_extract_expq __builtin_vsx_scalar_insert_exp_qp Builtins should behave the same way as in GCC. Differential Revision: https://reviews.llvm.org/D48185 llvm-svn: 342910
* Fix the type of 1<<31 integer constants.Benjamin Kramer2018-09-242-3/+3
| | | | | | | Shifting into the sign bit is technically undefined behavior. No known compiler exploits it though. llvm-svn: 342909
* [X86][AVX] Add truncation as shuffle test for PR31451Simon Pilgrim2018-09-241-0/+17
| | | | llvm-svn: 342908
* Reland r342494 after fixing LIT checks.Christy Lee2018-09-241-0/+60
| | | | llvm-svn: 342907
* [Analysis] add comment to generalize finding a scalar op from vector; NFCSanjay Patel2018-09-241-3/+4
| | | | llvm-svn: 342906
* [InstCombine] add/move tests for extractelement; NFCSanjay Patel2018-09-242-26/+82
| | | | llvm-svn: 342905
* [X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.Simon Pilgrim2018-09-244-125/+70
| | | | | | | | We're missing quite a bit of data for these instruction, removing the overrides makes this obvious - inconsistent reg/mem variants is a concern as well. Also, we have Divider resources (HWDivider etc.) but they aren't actually used consistently. llvm-svn: 342904
* [clangd] Fix uninit bool in r342888Sam McCall2018-09-241-1/+1
| | | | llvm-svn: 342903
* [InstCombine] improve variable name and use 'match'; NFCSanjay Patel2018-09-241-13/+15
| | | | | | | | | | | 'width' of a vector usually refers to the bit-width. https://bugs.llvm.org/show_bug.cgi?id=39016 shows a case where we could extend this fold to handle a case where the number of elements in the bitcasted vector is not equal to the resulting value. llvm-svn: 342902
* Reverting r342895Luke Cheeseman2018-09-245-43/+2
| | | | | | - The used builtins do not compile for pre arm v8.3a targets with gcc llvm-svn: 342901
* [ARM] Adjust the cost model for ExynosEvandro Menezes2018-09-241-2/+2
| | | | | | | Tune `MaxInterleaveFactor` and `LdStMultipleTiming`and remove `PartialUpdateClearance` for the Exynos processors. llvm-svn: 342900
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-09-241-0/+2
| | | | | | Enable crypto and literals fusion for the Exynos processors. llvm-svn: 342899
* [Thumb1] Any imm8 should have cost of 1Zhaoshi Zheng2018-09-242-2/+41
| | | | | | | | | A simple MOVS rd, imm8 can materialize [-128, 127] in signed i8 type or [0, 255] in unsigned i8 type on Thumb1. Differential Revision: https://reviews.llvm.org/D52257 llvm-svn: 342898
* [python] [tests] Update test_code_completionMichal Gorny2018-09-241-4/+4
| | | | | | | | Update expected completions to match output generated by clang-7.0. Differential Revision: https://reviews.llvm.org/D50171 llvm-svn: 342897
* [New PM][PassInstrumentation] IR printing support for New Pass ManagerFedor Sergeev2018-09-2413-43/+236
| | | | | | | | | | | | | | | | Implementing -print-before-all/-print-after-all/-filter-print-func support through PassInstrumentation callbacks. - PrintIR routines implement printing callbacks. - StandardInstrumentations class provides a central place to manage all the "standard" in-tree pass instrumentations. Currently it registers PrintIR callbacks. Reviewers: chandlerc, paquette, philip.pfaffe Differential Revision: https://reviews.llvm.org/D50923 llvm-svn: 342896
* [AArch64] Unwinding support for return address signingLuke Cheeseman2018-09-245-2/+43
| | | | | | | | | | - When return address signing is enabled, the LR may be signed on function entry - When an exception is thrown the return address is inspected used to unwind the call stack - Before this happens, the return address must be correctly authenticated to avoid causing an abort by dereferencing the signed pointer Differential Revision: https://reviews.llvm.org/D51432 llvm-svn: 342895
* [lld-link] Generalize handling of /debug and ↵Will Wilson2018-09-246-30/+92
| | | | | | | | | | | | | /debug:{none,full,fastlink,ghash,symtab} Implement final argument precedence if multiple /debug arguments are passed on the command-line to match expected link.exe behavior. Support /debug:none and emit warning for /debug:fastlink with automatic fallback to /debug:full. Emit error if last /debug:option is unknown. Emit warning if last /debugtype:option is unknown. https://reviews.llvm.org/D50404 llvm-svn: 342894
* Revert "rL342883: [Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with ↵Kristina Brooks2018-09-243-75/+26
| | | | | | | | `-fconstant-cfstrings`." Seems to be causing buildbot failures, need to look into it. llvm-svn: 342893
* [X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)Simon Pilgrim2018-09-2417-402/+212
| | | | | | | | Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases. This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions. llvm-svn: 342892
* [Arm][AsmParser] Restrict register list size for VSTM/VLDMLuke Cheeseman2018-09-242-0/+24
| | | | | | | | | | - The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified - The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers - This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389 Differential Revision: https://reviews.llvm.org/D52082 llvm-svn: 342891
* [CFString][ELF] Fix a missed test causing buildbot failures from 342883.Kristina Brooks2018-09-241-2/+2
| | | | | | Accidetanlly forgot to update it, big sorry. llvm-svn: 342890
* [VFS] Use llvm::StringMap instead of std::map. NFCEric Liu2018-09-241-1/+1
| | | | llvm-svn: 342889
* [clangd] Do bounds checks while reading data, otherwise var-length records ↵Sam McCall2018-09-241-139/+138
| | | | | | are too painful. NFC llvm-svn: 342888
* Correct RISC-V link in release notesEd Maste2018-09-241-1/+1
| | | | llvm-svn: 342887
* [DAGCombiner] use UADDO to optimize saturated unsigned addSanjay Patel2018-09-243-22/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preliminary step towards solving PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 If we have an 'add' instruction that sets flags, we can use that to eliminate an explicit compare instruction or some other instruction (cmn) that sets flags for use in the later select. As shown in the unchanged tests that use 'icmp ugt %x, %a', we're effectively reversing an IR icmp canonicalization that replaces a variable operand with a constant: https://rise4fun.com/Alive/V1Q But we're not using 'uaddo' in those cases via DAG transforms. This happens in CGP after D8889 without checking target lowering to see if the op is supported. So AArch already shows 'uaddo' codegen for the i8/i16/i32/i64 test variants with "using_cmp_sum" in the title. That's the pattern that CGP matches as an unsigned saturated add and converts to uaddo without checking target capabilities. This patch is gated by isOperationLegalOrCustom(ISD::UADDO, VT), so we see only see AArch diffs for i32/i64 in the tests with "using_cmp_notval" in the title (unlike x86 which sees improvements for all sizes because all sizes are 'custom'). But the AArch code (like x86) looks better when translated to 'uaddo' in all cases. So someone that is involved with AArch may want to set i8/i16 to 'custom' for UADDO, so this patch will fire on those tests. Another possibility given the existing behavior: we could remove the legal-or-custom check altogether because we're assuming that a UADDO sequence is canonical/optimal before we ever reach here. But that seems like a bug to me. If the target doesn't have an add-with-flags op, then it's not likely that we'll get optimal DAG combining using a UADDO node. This is similar justification for why we don't canonicalize IR to the overflow math intrinsic sibling (llvm.uadd.with.overflow) for UADDO in the first place. Differential Revision: https://reviews.llvm.org/D51929 llvm-svn: 342886
* Revert "We allow implicit function declarations as an extension in all C ↵Anastasia Stulova2018-09-244-6/+10
| | | | | | | | | | dialects. Remove OpenCL special case." Discussed on cfe-commits (Week-of-Mon-20180820), this change leads to the generation of invalid IR for OpenCL without giving an error. Therefore, the conclusion was to revert. llvm-svn: 342885
* [Mips][FastISel] Fix selectBranch on icmp i1Petar Jovanovic2018-09-242-0/+194
| | | | | | | | | | | | | | The r337288 tried to fix result of icmp i1 when its input is not sanitized by falling back to DagISel. While it now produces the correct result for bit 0, the other bits can still hold arbitrary value which is not supported by MipsFastISel branch lowering. This patch fixes the issue by falling back to DagISel in this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D52045 llvm-svn: 342884
* [Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with `-fconstant-cfstrings`.Kristina Brooks2018-09-242-24/+73
| | | | | | | | | | | | | | | | | | | [Clang][CodeGen][ObjC]: Fix non-bridged CoreFoundation builds on ELF targets that use `-fconstant-cfstrings`. The original changes from differential for a similar patch to PE/COFF (https://reviews.llvm.org/D44491) did not check for an edge case where the global could be a constant which surfaced as an issue when building for ELF because of different linkage semantics. This patch addresses several issues with crashes related to CF builds on ELF as well as improves data layout by ensuring string literals that back the actual CFConstStrings end up in .rodata in line with Mach-O. Change itself tested with CoreFoundation on Linux x86_64 but should be valid for BSD-like systems as well that use ELF as the native object format. Differential Revision: https://reviews.llvm.org/D52344 llvm-svn: 342883
* [PowerPC] Support operand modifier 'x' in inline asmZaara Syeda2018-09-242-0/+37
| | | | | | | | | | | gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882
* [dsymutil] Set LSan blacklist whenever sanitizers are enabled.Jonas Devlieghere2018-09-241-1/+1
| | | | | | | | LSan can be enabled by itself or as part of the address sanitizer. Rather than checking the enabled sanitizers for both, just set the LSan env options whenever a sanitizer is enabled. llvm-svn: 342881
* [NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constantsRoman Lebedev2018-09-242-0/+189
| | | | | | | | | | It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
* AMDGPU: Fix private handling for allowsMisalignedMemoryAccessesMatt Arsenault2018-09-243-35/+34
| | | | | | | | | | | | | If the alignment is at least 4, this should report true. Something still seems off with how < 4-byte types are handled here though. Fixing this seems to change how some combines get to where they get, but somehow isn't changing the net result. llvm-svn: 342879
* Fix some missing opcodes in bcanalyzerMatt Arsenault2018-09-242-0/+19
| | | | llvm-svn: 342878
* [llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFCAndrea Di Biagio2018-09-242-15/+25
| | | | llvm-svn: 342877
* Fix Wundef NDEBUG warning; NFCSven van Haastregt2018-09-241-1/+1
| | | | | | | Check for definedness of the NDEBUG macro rather than its value, to be consistent with other uses. llvm-svn: 342876
* Add NativeProcessProtocol unit testsPavel Labath2018-09-242-0/+156
| | | | | | | | | | | | | | | | | | | | | | Summary: NativeProcessProtocol is an abstract class, but it still contains a significant amount of code. Some of that code is tested via tests of specific derived classes, but these tests don't run everywhere, as they are OS and arch-specific. They are also relatively high-level, which means some functionalities (particularly the failure cases) are hard/impossible to test. In this approach, I replace the abstract methods with mocks, which allows me to inject failures into the lowest levels of breakpoint setting code and test the class behavior in this situation. Reviewers: zturner, teemperor Subscribers: mgorny, lldb-commits Differential Revision: https://reviews.llvm.org/D52152 llvm-svn: 342875
* [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33Sjoerd Meijer2018-09-244-6/+26
| | | | | | | | | | | | A sequence of VMUL and VADD instructions always give the same or better performance than a fused VMLA instruction on the Cortex-M4 and Cortex-M33. Executing the VMUL and VADD back-to-back requires the same cycles, but having separate instructions allows scheduling to avoid the hazard between these 2 instructions. Differential Revision: https://reviews.llvm.org/D52289 llvm-svn: 342874
* Revert r341932 "[ARM] Enable ARMCodeGenPrepare by default"Hans Wennborg2018-09-241-1/+1
| | | | | | | | | | | This caused miscompilation of WebRTC for Android: PR39060. > We've had the pass enabled downstream for a couple of weeks and it > seems to be okay, so enable it by default. > > Differential Revision: https://reviews.llvm.org/D51920 llvm-svn: 342873
* [ARM][ARMLoadStoreOptimizer]Luke Cheeseman2018-09-242-0/+54
| | | | | | | | | | | - The load store optimizer is currently merging multiple loads/stores into VLDM/VSTM with more than 16 doubleword registers - This is an UNPREDICTABLE instruction and shouldn't be done - It looks like the Limit for how many registers included in a merge got dropped at some point so I am reintroducing it in this patch - This fixes https://bugs.llvm.org/show_bug.cgi?id=38389 Differential Revision: https://reviews.llvm.org/D52085 llvm-svn: 342872
* [deadargelim] Update dbg.value of 'unused' parametersPetar Jovanovic2018-09-242-3/+94
| | | | | | | | | | | | DeadArgElim pass marks unused function arguments as ‘undef’ without updating existing dbg.values referring to it. As a consequence the debug info metadata in the final executable was wrong. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D51968 llvm-svn: 342871
* [ARM] bottom-top mul support ARMParallelDSPSam Parker2018-09-244-27/+712
| | | | | | | | | | | | | | | | Originally committed in rL342210 but was reverted in rL342260 because it was causing issues in vectorized code, because I had forgotten to ensure that we're operating on scalar values. Original commit message: On failing to find sequences that can be converted into dual macs, try to find sequential 16-bit loads that are used by muls which we can then use smultb, smulbt, smultt with a wide load. Differential Revision: https://reviews.llvm.org/D51983 llvm-svn: 342870
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