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* Make ptx barrier work irrespective of the cl_mem_fence_flagsJeroen Ketema2017-10-091-3/+1
| | | | | | | | | | | | This generates a "bar.sync 0” instruction, which not only causes the threads to wait, but does acts as a memory fence, as required by OpenCL. The fence does not differentiate between local and global memory. Unfortunately, there is no similar instruction which does not include a memory fence. Hence, we cannot optimize the case where neither CLK_LOCAL_MEM_FENCE nor CLK_GLOBAL_MEM_FENCE is passed. llvm-svn: 315228
* [sanitizer] Don't intercept signal and sigaction on FuchsiaPetr Hosek2017-10-092-1/+5
| | | | | | | | | Fuchsia doesn't support signals, so don't use interceptors for signal or sigaction. Differential Revision: https://reviews.llvm.org/D38669 llvm-svn: 315227
* [globalisel] Add support for ValueType operands in patterns.Daniel Sanders2017-10-092-33/+62
| | | | | | | | | | | | It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
* [MC] Use a unique_ptr<MCAssembler> for MCObjectStreamer's Assembler member.Lang Hames2017-10-092-4/+3
| | | | | | Removes manual new/delete. llvm-svn: 315225
* [InstCombine] fix formatting; NFCSanjay Patel2017-10-091-9/+7
| | | | llvm-svn: 315223
* Fix after r315079Adrian McCarthy2017-10-091-1/+1
| | | | | | | | | | | | Microsoft's debug implementation of std::copy checks if the destination is an array and then does some bounds checking. This was causing an assertion failure in fs::rename_internal which copies to a buffer of the appropriate size but that's type-punned to an array of length 1 for API compatibility reasons. Fix is to make make the destination a pointer rather than an array. llvm-svn: 315222
* Update ABISysV_arm64::RegisterIsVolatile to accept registers prefixed with rStephane Sezer2017-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: While the specification says that the 64bit registers are prefixed with `x`, it seems that many people still use `r`. Until recently, we had been using the `r` prefix instead of the `x` prefix in ds2. This caused lldb to fail during unwinding. I think it's reasonable to check for a register prefixed with `r`, since some people still choose to use `r`. Reviewers: sas, fjricci, clayborg Reviewed By: sas, clayborg Subscribers: aemerson, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38376 Change by Alex Langford <apl@fb.com> llvm-svn: 315221
* [ubsan] Disable one test on Android.Evgeniy Stepanov2017-10-091-0/+2
| | | | llvm-svn: 315220
* AMDGPU: Fix missing declaration for __builtin_amdgcn_dispatch_ptrMatt Arsenault2017-10-092-0/+8
| | | | llvm-svn: 315219
* [dsymutil] Emit valid debug locations when no symbol flags are setFrancis Ricci2017-10-094-1/+40
| | | | | | | | | | | | | | | | | Summary: swiftc emits symbols without flags set, which led dsymutil to ignore them when searching for global symbols, causing dwarf location data to be omitted. Xcode's dsymutil handles this case correctly, and emits valid location data. Add this functionality to llvm-dsymutil by allowing parsing of symbols with no flags set. Reviewers: aprantl, friss, JDevlieghere Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38587 llvm-svn: 315218
* [SLP] Test for wrongly vectorized set of extractelements, NFC.Alexey Bataev2017-10-091-0/+30
| | | | llvm-svn: 315217
* Limit CFI blacklist entries to specific CFI modeVlad Tsyrklevich2017-10-091-0/+1
| | | | | | | | | | | | | | | | | Summary: Since D37924 and D37925 were merged, it's now possible to specify individual sanitizers or CFI modes in sanitizer blacklists. Update the CFI blacklist entries to only apply to cfi-unrelated-cast checks. Reviewers: eugenis, pcc Reviewed By: eugenis Subscribers: kcc Differential Revision: https://reviews.llvm.org/D38385 llvm-svn: 315216
* Make the cfi target available on more platforms.Peter Collingbourne2017-10-092-31/+32
| | | | | | | | On non-Linux targets it just installs the blacklist. Differential Revision: https://reviews.llvm.org/D38661 llvm-svn: 315215
* [clangd] Added a command-line arg to mirror clangd input into a file.Ilya Biryukov2017-10-094-14/+208
| | | | | | | | | | | | | | Summary: The arg is useful for debugging and creating test cases. Reviewers: bkramer, krasimir Reviewed By: bkramer Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D37970 llvm-svn: 315214
* [clangd] Added a test for r315212.Ilya Biryukov2017-10-091-0/+15
| | | | llvm-svn: 315213
* Set PreprocessorOpts.GeneratePreamble=true in PrecompiledPreamble.Ilya Biryukov2017-10-092-1/+2
| | | | | | | | | | | | | | | | Summary: It was previsouly set only in ASTUnit, but it should be set for all client of PrecompiledPreamble. Reviewers: erikjv, bkramer, klimek Reviewed By: bkramer Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D38617 llvm-svn: 315212
* [clangd] Added move-only function helpers.Ilya Biryukov2017-10-093-9/+144
| | | | | | | | | | | | | | | | | | | Summary: They are now used in ClangdScheduler instead of deferred std::async computations. The results of `std::async` are much less effective and do not provide a good abstraction for similar purposes, i.e. for storing additional callbacks to clangd async tasks. The actual callback API will follow a bit later. Reviewers: klimek, bkramer, sammccall, krasimir Reviewed By: sammccall Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D38627 llvm-svn: 315210
* [TableGen] remove make_range where not necessaryJaved Absar2017-10-091-6/+5
| | | | llvm-svn: 315209
* [llvm-rc] Have the tokenizer discard single & block comments.Zachary Turner2017-10-094-0/+72
| | | | | | | | | | This allows rc files to have comments. Eventually we should just use clang's c preprocessor, but that's a bit larger effort for minimal gain, and this is straightforward. Differential Revision: https://reviews.llvm.org/D38651 llvm-svn: 315207
* [DAG] combine assertsexts around a truncSanjay Patel2017-10-098-62/+83
| | | | | | | This was a suggested follow-up to: D37017 / https://reviews.llvm.org/rL313577 llvm-svn: 315206
* [AArch64] Improve codegen for inverted overflow checking intrinsicsAmara Emerson2017-10-092-9/+171
| | | | | | | | | | | | | | E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the inverted condition code for the CSEL. rdar://28495949 Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D38160 llvm-svn: 315205
* [x86] regenerate test checks; NFCSanjay Patel2017-10-091-90/+115
| | | | llvm-svn: 315204
* [AArch64] fix typos in test assertionsSanjay Patel2017-10-091-2/+2
| | | | llvm-svn: 315203
* [X86] Remove a setLoadExtAction from the AVX512 section that uses an ↵Craig Topper2017-10-091-1/+0
| | | | | | AVX512BW type and is alraedy present in the AVX512BW section. llvm-svn: 315202
* [X86] Enable extended comparison predicate support for SETUEQ/SETONE when ↵Craig Topper2017-10-097-114/+56
| | | | | | | | | | targeting AVX instructions. We believe that despite AMD's documentation, that they really do support all 32 comparision predicates under AVX. Differential Revision: https://reviews.llvm.org/D38609 llvm-svn: 315201
* [DWARFDIE] Rewrite `operator !=` using `operator ==`. NFCI.Davide Italiano2017-10-091-1/+1
| | | | llvm-svn: 315200
* [SymbolFile/DWARF] Simplify two functions. NFCI.Davide Italiano2017-10-091-8/+2
| | | | llvm-svn: 315199
* Certain versions of clang require an explicit initialization for literal ↵Benjamin Kramer2017-10-081-1/+1
| | | | | | | | | | const members. include/clang/Lex/PreprocessorLexer.h:79:3: error: constructor for 'clang::PreprocessorLexer' must explicitly initialize the const member 'FID' llvm-svn: 315197
* Remove unused variables. No functionality change.Benjamin Kramer2017-10-089-12/+0
| | | | llvm-svn: 315196
* [X86][SSE] Don't call combineTo inside combineX86ShufflesRecursively. NFCI.Simon Pilgrim2017-10-081-51/+60
| | | | | | | | Return the combined shuffle from combineX86ShufflesRecursively and perform the combineTo in the caller. Makes it easier for future patches to use this in functions that aren't actually shuffles themselves. llvm-svn: 315195
* Make SourceLocation, QualType and friends have constexpr constructors.Benjamin Kramer2017-10-083-18/+16
| | | | | | No functionality change intended. llvm-svn: 315194
* travis: Make sure we report failure even if only earlier checked files failJan Vesely2017-10-081-3/+5
| | | | | | | | | | for loop would only report status of the last command v2: return '1' call test instead of '[' Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315193
* check_external_calls.sh: Print number of calls in tested file.Jan Vesely2017-10-081-2/+3
| | | | | | Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315192
* ptx: Use __clc_nextafter to implement nextafterJan Vesely2017-10-082-0/+11
| | | | | | | | using clang builtin results in external library call Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315191
* Do not include clc_nextafter header globallyJan Vesely2017-10-084-16/+3
| | | | | | | | Drop unused clc/math/clc_nextafter.h header Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315190
* math/nextafter: Use custom declaration inc fileJan Vesely2017-10-082-4/+2
| | | | | | Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315189
* math/binary_decl.inc: Do not declare mixed float/double functionsJan Vesely2017-10-081-5/+1
| | | | | | | | fmin/fmax only need vector/scalar mix Reviewer: Jeroen Ketema Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 315188
* Tidyup with clang-format. NFCI.Simon Pilgrim2017-10-081-8/+5
| | | | llvm-svn: 315187
* [X86][SSE] Add test case for PR27708Simon Pilgrim2017-10-081-0/+142
| | | | llvm-svn: 315186
* Remove unused variables. No functionality change.Benjamin Kramer2017-10-0815-18/+2
| | | | llvm-svn: 315185
* [X86] Regenerate fast-isel-select-pseudo-cmov.ll to prepare for D38609.Craig Topper2017-10-081-64/+213
| | | | llvm-svn: 315184
* [TableGen] Simplify, add range_loop in CodeGenScheduleJaved Absar2017-10-081-11/+10
| | | | llvm-svn: 315183
* [X86] getTargetConstantBitsFromNode - add support for decoding scalar constantsSimon Pilgrim2017-10-082-6/+11
| | | | llvm-svn: 315182
* [X86] Prefer MOVSS/SD over BLENDI during legalization. Remove BLENDI ↵Craig Topper2017-10-084-94/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | versions of scalar arithmetic patterns Summary: We currently disable some converting of shuffles to MOVSS/MOVSD during legalization if SSE41 is enabled. But later during shuffle combining we go back to prefering MOVSS/MOVSD. Additionally we have patterns that look for BLENDIs to detect scalar arithmetic operations. I believe due to the combining using MOVSS/MOVSD these are unnecessary. Interestingly, we still codegen blend instructions even though lowering/isel emit movss/movsd instructions. Turns out machine CSE commutes them to blend, and then commuting those blends back into blends that are equivalent to the original movss/movsd. This patch fixes the inconsistency in legalization to prefer MOVSS/MOVSD. The one test change was caused by this change. The problem is that we have integer types and are mostly selecting integer instructions except for the shufps. This shufps forced the execution domain, but the vpblendw couldn't have its domain changed with a naive instruction swap. We could fix this by special casing VPBLENDW based on the immediate to widen the element type. The rest of the patch is removing all the excess scalar patterns. Long term we should probably add isel patterns to make MOVSS/MOVSD emit blends directly instead of relying on the double commute. We may also want to consider emitting movss/movsd for optsize. I also wonder if we should still use the VEX encoded blendi instructions even with AVX512. Blends have better throughput, and that may outweigh the register constraint. Reviewers: RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38023 llvm-svn: 315181
* Make more constructors constexpr or use =default.Benjamin Kramer2017-10-087-13/+14
| | | | | | | This lets the compiler reason about the type more easily. No functionality change intended. llvm-svn: 315180
* [AArch64][GlobalISel] Add a test case for G_PHI of p0 instruction selection.Amara Emerson2017-10-081-0/+45
| | | | llvm-svn: 315179
* [AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.Amara Emerson2017-10-081-0/+42
| | | | llvm-svn: 315178
* [AArch64][GlobalISel] Make G_PHI of p0 types legal.Amara Emerson2017-10-082-1/+52
| | | | | | Differential Revision: https://reviews.llvm.org/D38621 llvm-svn: 315177
* [X86][XOP] Add XOP oddshuffles testsSimon Pilgrim2017-10-081-0/+266
| | | | | | XOP codegen is often different to generic AVX - thank you vpperm! llvm-svn: 315176
* [X86][SKX] Adding the scheduling information for the SKX target.Gadi Haber2017-10-0816-5525/+12477
| | | | | | | | | | | | | | | | | | Adding the scheduling information for the SkylakeServer (SKX) target. This patch adds the instruction scheduling information for the SkylakeServer (SKX) architecture target by adding the file X86SchedSkylakeServer.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r310792, the HSW target in r311879 and the SkylakeClient (SKL) target in rL313613. Please expect some performance fluctuations due to code alignment effects. Reviewers: zvi, RKSimon, craig.topper, chandlerc, aymanmu Differential Revision: https://reviews.llvm.org/D38443 Change-Id: I5c228fcc09e9e5a99b6116e62b356c4f9b971185 llvm-svn: 315175
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