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* Fix an edge case with BinaryOperator's in -Wuninitialized. Add testcases forRichard Trieu2014-09-242-2/+20
| | | | | | the other visitors as well. llvm-svn: 218366
* Follow-up to r218292: Add more REVERTIBLE_TYPE_TRAITs.Nico Weber2014-09-244-6/+168
| | | | | | | | | r218292 reverted r197496 because it broke things. In addition to breaking things, r197496 also made all traits starting with __is_ revertible. Reinstantiate that part of r197496 because code out there (e.g. libc++) depends on this behavior. Fixes PR21045. llvm-svn: 218365
* Clear PreferredExtendType for in each function-specific state ↵Jiangning Liu2014-09-241-0/+1
| | | | | | FunctionLoweringInfo. llvm-svn: 218364
* [x86] More refactoring of the shuffle comment emission. The previousChandler Carruth2014-09-241-38/+38
| | | | | | | | | | | attempt didn't work out so well. It looks like it will be much better for introducing extra logic to find a shuffle mask if the finding logic is totally separate. This also makes it easy to sink the opcode logic completely out of the routine so we don't re-dispatch across it. Still no functionality changed. llvm-svn: 218363
* [x86] Bypass the shuffle mask comment generation when not using verboseChandler Carruth2014-09-241-0/+2
| | | | | | | | asm. This can be somewhat expensive and there is no reason to do it outside of tests or debugging sessions. I'm also likely to make it significantly more expensive to support more styles of shuffles. llvm-svn: 218362
* [x86] Hoist the logic for extracting the relevant bits of informationChandler Carruth2014-09-241-16/+20
| | | | | | | | | | | | | | | from the MachineInstr into the caller which is already doing a switch over the instruction. This will make it more clear how to compute different operands to feed the comment selection for example. Also, in a drive-by-fix, don't append an empty comment string (which is a no-op ultimately). No functionality changed. llvm-svn: 218361
* R600/SI: Add new helper isSGPRClassIDMatt Arsenault2014-09-242-8/+14
| | | | | | Move these into header since they are trivial llvm-svn: 218360
* R600/SI: Fix hardcoded and wrong operand numbers.Matt Arsenault2014-09-241-5/+3
| | | | | | Also fix leftover debug printing llvm-svn: 218359
* R600/SI: Enable named operand table for SALU instructionsMatt Arsenault2014-09-241-0/+8
| | | | llvm-svn: 218358
* [x86] Start refactoring the comment printing logic in the MC lowering ofChandler Carruth2014-09-241-87/+102
| | | | | | | | | | | | | | | vector shuffles. This is just the beginning by hoisting it into its own function and making use of early exit to dramatically simplify the flow of the function. I'm going to be incrementally refactoring this until it is a bit less magical how this applies to other instructions, and I can teach it how to dig a shuffle mask out of a register. Then I plan to hook it up to VPERMD so we get our mask comments for it. No functionality changed yet. llvm-svn: 218357
* R600/SI: Fix weird CHECK-DAG usageMatt Arsenault2014-09-242-4/+4
| | | | | | This prevents these from failing in a future commit. llvm-svn: 218356
* [PECOFF] Exported name should match C++ mangled nameRui Ueyama2014-09-243-21/+46
| | | | | | | | | | | | | | Currently you can omit the leading underscore from exported symbol name. LLD will look for mangled name for you. But it won't look for C++ mangled name. This patch is to support that. If "sym" is specified to be exported, the linker looks for not only "sym", but also "_sym" and "?sym@@<whatever>", so that you can export a C++ function without decorating it. llvm-svn: 218355
* [PECOFF] Keep renamed undefined symbol name in export descriptorRui Ueyama2014-09-242-14/+7
| | | | | | | | | | | | | | | | | Exported symbol name resolution is two-pass. In the first pass, we try to resolve that as a regular undefined symbol. If it fails, we look for mangled name for the symbol and rename the undefined symbol and try again. After all name resolution is done, we look for an atom for each exported symbol again, to construct the export table. In this process we try the regular names first, and then try mangled names. But at this moment we should have knew which name is correct. This patch is to keep the information we get in the first process to use it later. llvm-svn: 218354
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-248-63/+69
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
* R600/SI: Move PHIs that define SGPRs to the VALU in most casesTom Stellard2014-09-241-0/+52
| | | | | | | This fixes a bug that is uncovered by a future commit and will be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case. llvm-svn: 218352
* R600/SI: Fix the FixSGPRLiveRanges passTom Stellard2014-09-244-33/+121
| | | | | | | | | | | The previous implementation was extending the live range of SGPRs by modifying the live intervals directly. This was causing a lot of machine verification errors when the machine scheduler was enabled. The new implementation adds pseudo instructions with implicit uses to extend the live ranges of SGPRs, which works much better. llvm-svn: 218351
* R600/SI: Mark EXEC_LO and EXEC_HI as reservedTom Stellard2014-09-241-0/+6
| | | | | | | These registers can be allocated and used like other 32-bit registers, but it seems like a likely source for bugs. llvm-svn: 218350
* R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-09-241-1/+10
| | | | | | | | Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO, VCC_HI, and M0. The previous implementation would assertion fail when passed these registers. llvm-svn: 218349
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-248-48/+332
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* [x86] Teach the new vector shuffle lowering to lower v8i32 shuffles withChandler Carruth2014-09-242-272/+646
| | | | | | | | | | | | the native AVX2 instructions. Note that the test case is really frustrating here because VPERMD requires the mask to be in the register input and we don't produce a comment looking through that to the constant pool. I'm going to attempt to improve this in a subsequent commit, but not sure if I will succeed. llvm-svn: 218347
* [x86] Fix a really terrible bug in the repeated 128-bin-lane shuffleChandler Carruth2014-09-242-18/+41
| | | | | | | | | | | | detection. It was incorrectly handling undef lanes by actually treating an undef lane in the first 128-bit lane as a *numeric* shuffle value. Fortunately, this almost always DTRT and disabled detecting repeated patterns. But not always. =/ This patch introduces a much more principled approach and fixes the miscompiles I spotted by inspection previously. llvm-svn: 218346
* [PECOFF] Keep unmangled name in the export table descriptorRui Ueyama2014-09-243-13/+3
| | | | | | | | | | | | | | | | | The export table descriptor is a data structure to keep information about the export table. It contains a symbol name, and the name may or may not be mangled. We need unmangled names for the export table, so we demangle them before writing them to the export table. Obviously this is not a correct round-trip conversion. That could drop a leading underscore from a symbol because that's indistinguishable from a mangled name. What we need to do is to keep unmangled names. This patch does that. llvm-svn: 218345
* [PECOFF] Simplify /machine option handlingRui Ueyama2014-09-243-11/+5
| | | | | | | | /machine:ebc was previously recognized but rejected. Unknown architecture names were handled differently but eventually rejected too. We don't need to distinguish them. llvm-svn: 218344
* [PECOFF] Change export table type.Rui Ueyama2014-09-244-38/+47
| | | | | | | | | This patch changes the type of export table set from std::set to std::vector. The new code is slightly inefficient, but because export table elements are actually mutable, std::vector is better here. No functionality change. llvm-svn: 218343
* [PECOFF] Fix duplicate /export optionsRui Ueyama2014-09-233-15/+9
| | | | | | | | | If two or more /export options are given for the same symbol, we should always print a warning message and use the first one regardless of other parameters. Previously there was a case that the first parameter is not used. llvm-svn: 218342
* Fix swift-atomics testcaseRobin Morisset2014-09-231-0/+6
| | | | | | | | | This testcase was not testing what it meant: because there were only two checks for dmb {{ish}} in the second function, it could have missed a bug where one of the three required dmb {{ish}} became dmb {{ishst}}. As I was fixing it, I also added CHECK-LABELs to make it a bit less brittle. llvm-svn: 218341
* MS ABI: Pure virtual functions don't contribute to vtordispsDavid Majnemer2014-09-232-14/+39
| | | | | | | | | | | Usually, overriding a virtual function defined in a virtual base required emission of a vtordisp slot in the record. However no vtordisp is needed if the overriding function is pure; it should be impossible to observe the pure virtual method. This fixes PR21046. llvm-svn: 218340
* Improve -Wuninitialized to take into account field ordering with initializerRichard Trieu2014-09-234-4/+142
| | | | | | | lists. Since the fields are inititalized one at a time, using a field with lower index to initialize a higher indexed field should not be warned on. llvm-svn: 218339
* [x86] Teach the new vector shuffle lowering to lower v4i64 vectorChandler Carruth2014-09-233-139/+311
| | | | | | | | | | | shuffles using the AVX2 instructions. This is the first step of cutting in real AVX2 support. Note that I have spotted at least one bug in the test cases already, but I suspect it was already present and just is getting surfaced. Will investigate next. llvm-svn: 218338
* GlobalOpt: Preserve comdats of unoptimized initializersReid Kleckner2014-09-232-45/+63
| | | | | | | | | | | | | Rather than slurping in and splatting out the whole ctor list, preserve the existing array entries without trying to understand them. Only remove the entries that we know we can optimize away. This way we don't need to wire through priority and comdats or anything else we might add. Fixes a linker issue where the .init_array or .ctors entry would point to discarded initialization code if the comdat group from the TU with the faulty global_ctors entry was dropped. llvm-svn: 218337
* AArch64: allow constant expressions for shifted reg literalsJim Grosbach2014-09-232-6/+19
| | | | | | | | | | | | e.g., add w1, w2, w3, lsl #(2 - 1) This sort of thing comes up in pre-processed assembly playing macro games. Still validate that it's an assembly time constant. The early exit error check was just a bit overzealous and disallowed a left paren. rdar://18430542 llvm-svn: 218336
* [x86] Teach the rest of the 'target shuffle' machinery about blends andChandler Carruth2014-09-234-13/+42
| | | | | | | | | | | add VPBLENDD to the InstPrinter's comment generation so we get nice comments everywhere. Now that we have the nice comments, I can see the bug introduced by a silly typo in the commit that enabled VPBLENDD, and have fixed it. Yay tests that are easy to inspect. llvm-svn: 218335
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-238-67/+149
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* PR18793: If we try to EnterTokenStream when our current lexer is a cachingRichard Smith2014-09-233-0/+25
| | | | | | | | | lexer, add the token buffer underneath the caching lexer where possible and push the tokens directly into the caching lexer otherwise. We previously put the lexer into a corrupted state where we could not guarantee to provide the tokens in the right order and would sometimes assert. llvm-svn: 218333
* [X86] Make wide loads be managed by AtomicExpandRobin Morisset2014-09-233-32/+41
| | | | | | | | | | | | | | | | | | | | | | | Summary: AtomicExpand already had logic for expanding wide loads and stores on LL/SC architectures, and for expanding wide stores on CmpXchg architectures, but not for wide loads on CmpXchg architectures. This patch fills this hole, and makes use of this new feature in the X86 backend. Only one functionnal change: we now lose the SynchScope attribute. It is regrettable, but I have another patch that I will submit soon that will solve this for all of AtomicExpand (it seemed better to split it apart as it is a different concern). Test Plan: make check-all (lots of tests for this functionality already exist) Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5404 llvm-svn: 218332
* [Power] Use AtomicExpandPass for fence insertion, and use lwsync where ↵Robin Morisset2014-09-236-3/+178
| | | | | | | | | | | | | | | | | | | | | | | appropriate Summary: This patch makes use of AtomicExpandPass in Power for inserting fences around atomic as part of an effort to remove fence insertion from SelectionDAGBuilder. As a big bonus, it lets us use sync 1 (lightweight sync, often used by the mnemonic lwsync) instead of sync 0 (heavyweight sync) in many cases. I also added a test, as there was no test for the barriers emitted by the Power backend for atomic loads and stores. Test Plan: new test + make check-all Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5180 llvm-svn: 218331
* Don't perform ADL when looking up operator=; there is no non-member form ofRichard Smith2014-09-234-9/+24
| | | | | | | | | that function, and apart from being slow, this is unnecessary: ADL can trigger instantiations that are not permitted here. The standard isn't *completely* clear here, but this seems like the intent, and in any case this approach is permitted by [temp.inst]p7. llvm-svn: 218330
* Add AtomicExpandPass::bracketInstWithFences, and use it whenever ↵Robin Morisset2014-09-234-56/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getInsertFencesForAtomic would trigger in SelectionDAGBuilder Summary: The goal is to eventually remove all the code related to getInsertFencesForAtomic in SelectionDAGBuilder as it is wrong (designed for ARM, not really portable, works mostly by accident because the backends are overly conservative), and repeats the same logic that goes in emitLeading/TrailingFence. In this patch, I make AtomicExpandPass insert the fences as it knows better where to put them. Because this requires getting the fences and not just passing an IRBuilder around, I had to change the return type of emitLeading/TrailingFence. This code only triggers on ARM for now. Because it is earlier in the pipeline than SelectionDAGBuilder, it triggers and lowers atomic accesses to atomic so SelectionDAGBuilder does not add barriers anymore on ARM. If this patch is accepted I plan to implement emitLeading/TrailingFence for all backends that setInsertFencesForAtomic(true), which will allow both making them less conservative and simplifying SelectionDAGBuilder once they are all using this interface. This should not cause any functionnal change so the existing tests are used and not modified. Test Plan: make check-all, benefits from existing tests of atomics on ARM Reviewers: jfb, t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5179 llvm-svn: 218329
* [MCJIT] Fix some more RuntimeDyld debugging output format specifiers.Lang Hames2014-09-231-3/+3
| | | | llvm-svn: 218328
* [MCJIT] Remove PPCRelocations.h - it's no longer used.Lang Hames2014-09-231-56/+0
| | | | | | | This was overlooked in r218320, which removed the relocation headers for other targets. Thanks to Ulrich Weigand for catching it. llvm-svn: 218327
* Just add a fixme about a possibly faster implementation of some atomic loads ↵Robin Morisset2014-09-231-0/+3
| | | | | | on some ARM processors llvm-svn: 218326
* Fix up the HostThread interface, making the interface simpler.Zachary Turner2014-09-2319-134/+81
| | | | | | | Reviewed by: Greg Clayton Differential Revision: http://reviews.llvm.org/D5417 llvm-svn: 218325
* Fix typoMatt Arsenault2014-09-231-2/+3
| | | | llvm-svn: 218324
* Add ASan history threads into process_sp->GetExtendedThreadList, so they ↵Kuba Brecka2014-09-232-37/+41
| | | | | | | | don't get freed too early Reviewed at http://reviews.llvm.org/D5452 llvm-svn: 218323
* [x86] Teach the new shuffle lowering's blend functionality to use AVX2'sChandler Carruth2014-09-233-28/+47
| | | | | | | | | | | | | VPBLENDD where appropriate even on 128-bit vectors. According to Agner's tables, this instruction is significantly higher throughput (can execute on any port) on Haswell chips so we should aggressively try to form it when available. Sadly, this loses our delightful shuffle comments. I'll add those back for VPBLENDD next. llvm-svn: 218322
* Make -core/-flavor options have higher priority than linker nameRui Ueyama2014-09-232-16/+34
| | | | | | | | | Also allows -core/flavor to appear at any position in the command line. Patch from Oleg Ranevskyy! http://reviews.llvm.org/D5384 llvm-svn: 218321
* [MCJIT] Nuke MachineRelocation and MachineCodeEmitter. Now that the old JIT isLang Hames2014-09-238-902/+0
| | | | | | gone they're no longer needed. llvm-svn: 218320
* [docs] Fixed a typo in Atomics.rstJingyue Wu2014-09-231-4/+4
| | | | llvm-svn: 218319
* [MCJIT] Remove a few more references to JITMemoryManager that survived r218316.Lang Hames2014-09-234-10/+1
| | | | llvm-svn: 218318
* [MCJIT] Remove #include of JITMemoryManager that accidentally survived r218316.Lang Hames2014-09-231-1/+0
| | | | llvm-svn: 218317
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