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llvm-svn: 139079
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llvm-svn: 139078
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well.
Also, clean up the flow of the code a bit, and factor things more
nicely.
Finally, add the test case that was missing from my previous
commit (sorry), with new tests added to cover temporaries and other fun
cases.
llvm-svn: 139077
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values that the resume instruction uses.
PR10850
llvm-svn: 139076
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reference members of classes. We've had several bugs reported because of
this, and there's no reason not to flag it right away in the compiler.
Comments especially welcome on the strategy for implementing this
warning (IE, what should trigger this?) and on the text of the warning
itself.
I'm going to extend this to cover obvious cases with temporaries and
beef up the test cases some in subsequent patches. I'll then run it over
a large codebase and make sure its not misbehaving before I add it to
-Wall or turn it on by default. I think this one might be a good
candidate for on by default.
llvm-svn: 139075
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llvm-svn: 139074
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the cycle of missing AVX counterparts of already present SSE* patterns
llvm-svn: 139073
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llvm-svn: 139072
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llvm-svn: 139071
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llvm-svn: 139070
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llvm-svn: 139069
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duplicate it for AVX mode.
llvm-svn: 139068
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llvm-svn: 139067
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that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
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pattern should be matched
llvm-svn: 139065
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llvm-svn: 139064
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it!
llvm-svn: 139063
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llvm-svn: 139062
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llvm-svn: 139061
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OptForSize pattern
llvm-svn: 139060
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If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.
llvm-svn: 139059
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llvm-svn: 139058
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The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
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It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
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llvm-svn: 139055
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llvm-svn: 139054
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llvm-svn: 139053
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llvm-svn: 139052
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llvm-svn: 139051
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llvm-svn: 139050
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Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
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llvm-svn: 139048
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llvm-svn: 139047
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llvm-svn: 139046
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missing from fast-isel.
llvm-svn: 139044
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llvm-svn: 139043
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llvm-svn: 139042
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// rdar://10033896
llvm-svn: 139041
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For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
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llvm-svn: 139039
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llvm-svn: 139038
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llvm-svn: 139037
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llvm-svn: 139036
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slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.
llvm-svn: 139035
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Add a virtual method GetHardwareWatchpointHit() to the DNBArchProtocol base class
which consults the architecture to return the watchpoint hit; otherwise return an
invalid index.
Add impl. of the method to X86_64 and I386 subclasses, plus reset the debug status
register before we resume execution of the inferior thread.
llvm-svn: 139034
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llvm-svn: 139033
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llvm-svn: 139032
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Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names. We'll use this to
provide more programmability in how we name defs and their associated
members.
llvm-svn: 139031
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llvm-svn: 139029
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case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
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