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* Update for LLVM API rename of AttributeSet -> AttributeListReid Kleckner2017-03-211-5/+2
| | | | llvm-svn: 298399
* Fix RST docs AttributeList heading underlineReid Kleckner2017-03-211-1/+1
| | | | llvm-svn: 298398
* AMDGPU: Buffer descriptor changes for GFX9Marek Olsak2017-03-215-8/+23
| | | | | | | | | | Reviewers: arsenm Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr Differential Revision: https://reviews.llvm.org/D31158 llvm-svn: 298397
* AMDGPU: Always use VGPR indexing on GFX9Marek Olsak2017-03-214-3/+8
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr Differential Revision: https://reviews.llvm.org/D31157 llvm-svn: 298396
* [Hexagon] Add -march=hexagon to a testcaseKrzysztof Parzyszek2017-03-211-1/+1
| | | | llvm-svn: 298395
* Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner2017-03-2117-197/+180
| | | | llvm-svn: 298394
* Rename AttributeSet to AttributeListReid Kleckner2017-03-2194-920/+921
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This class is a list of AttributeSetNodes corresponding the function prototype of a call or function declaration. This class used to be called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is typically accessed by parameter and return value index, so "AttributeList" seems like a more intuitive name. Rename AttributeSetImpl to AttributeListImpl to follow suit. It's useful to rename this class so that we can rename AttributeSetNode to AttributeSet later. AttributeSet is the set of attributes that apply to a single function, argument, or return value. Reviewers: sanjoy, javed.absar, chandlerc, pete Reviewed By: pete Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits Differential Revision: https://reviews.llvm.org/D31102 llvm-svn: 298393
* [index/AST] Determine if a typedef shares a name and spelling location with ↵Argyrios Kyrtzidis2017-03-2110-6/+151
| | | | | | | | | | its underlying tag type In such a case, as when using the NS_ENUM macro, for indexing purposes treat the typedef as 'transparent', meaning we treat its references as symbols of the underlying tag symbol. Also provide a libclang API to check for such typedefs. llvm-svn: 298392
* [Modules] Find PrivateHeaders when looking into subframeworksBruno Cardoso Lopes2017-03-2112-7/+48
| | | | | | | | | Fix the current parsing of subframeworks in modulemaps to lookup for headers based on whether they are frameworks. rdar://problem/30563982 llvm-svn: 298391
* AMDGPU: Fix not including v2i16/v2f16 in register classMatt Arsenault2017-03-211-1/+1
| | | | llvm-svn: 298390
* Don't compose DWARF expressions with multiple subregisters.Adrian Prantl2017-03-212-0/+131
| | | | | | | | | If a register location can only be described by a complex expression (i.e., multiple subregisters) it doesn't safely compose with another complex expression. For example, it is not possible to apply a DW_OP_deref operation to multiple DW_OP_pieces. llvm-svn: 298389
* DwarfExpression: Defer emitting DWARF register operationsAdrian Prantl2017-03-212-23/+55
| | | | | | | | until the rest of the expression is known. This is still an NFC refactoring in preparation of a subsequent bugfix. llvm-svn: 298388
* AMDGPU: Fix asserting on 0 dmask for image intrinsicsMatt Arsenault2017-03-214-0/+409
| | | | | | Fold these to undef during lowering so users get eliminated. llvm-svn: 298387
* AMDGPU: Convert image intrinsic uses in testsMatt Arsenault2017-03-2114-208/+205
| | | | llvm-svn: 298386
* DAG: Fold bitcast/extract_vector_elt of undef to undefMatt Arsenault2017-03-214-8/+40
| | | | | | Fixes not eliminating store when intrinsic is lowered to undef. llvm-svn: 298385
* tsan: fix pie_no_aslr testDmitry Vyukov2017-03-211-0/+1
| | | | | | | It failed on clang-cmake-aarch64-39vma. Restrict it to x86_64 only. llvm-svn: 298383
* Revert r298274: "Use pthreads for thread-local lsan allocator cache on darwin"Chandler Carruth2017-03-214-56/+44
| | | | | | | | This fixes a failure currently present on the upstream linux boxes (and reproduces for me as well): http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/1130/steps/64-bit%20check-asan-dynamic/logs/stdio llvm-svn: 298382
* Fix shufpd test name.Simon Pilgrim2017-03-211-4/+4
| | | | llvm-svn: 298381
* [ARM] [Assembler] Support negative immediates for A32, T32 and T16Sanne Wouda2017-03-2111-33/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
* Test commit accessYi Kong2017-03-211-10/+10
| | | | | | Remove some trailing whitespaces. llvm-svn: 298379
* tsan: support __ATOMIC_HLE_ACQUIRE/RELEASE flagsDmitry Vyukov2017-03-212-1/+43
| | | | | | | | | | | HLE flags can be combined with memory order in atomic operations. Currently tsan runtime crashes on e.g. IsStoreOrder(mo) in atomic store if any of these additional flags are specified. Filter these flags out. See the comment as to why it is safe. llvm-svn: 298378
* [InstCombine] auto-generate better checks; NFCSanjay Patel2017-03-212-80/+122
| | | | llvm-svn: 298377
* [x86] use PMOVMSK for vector-sized equality comparisonsSanjay Patel2017-03-212-67/+63
| | | | | | | | | | We could do better by splitting any oversized type into whatever vector size the target supports, but I left that for future work if it ever comes up. The motivating case is memcmp() calls on 16-byte structs, so I think we can wire that up with a TLI hook that feeds into this. Differential Revision: https://reviews.llvm.org/D31156 llvm-svn: 298376
* Replace std::ofstream with llvm::raw_fd_ostreamPavel Labath2017-03-213-14/+22
| | | | | | | | | | | | | | Summary: ofstream does not handle paths with non-ascii characters correctly on windows, so I am switching these to llvm streams to fix that. Reviewers: zturner, eugene Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D31079 llvm-svn: 298375
* Remove ProcFileReaderPavel Labath2017-03-214-167/+25
| | | | | | | This removes the last usage of ProcFileReader from NativeProcessLinux and then deletes the class itself. llvm-svn: 298374
* Fixed intermittent hang on tests with "target teams if(0)" construct with no ↵Andrey Churbanov2017-03-212-6/+74
| | | | | | | | parallel inside. Differential Revision: https://reviews.llvm.org/D29597 llvm-svn: 298373
* tsan: add test for pie/no aslrDmitry Vyukov2017-03-211-0/+5
| | | | | | Just ensure that such combination works. llvm-svn: 298372
* [DOXYGEN] Improvements to smmintrin.h and emmintrin.h intrinsics.Ekaterina Romanova2017-03-212-13/+13
| | | | | | | | | | | I made some small changes in smmintrin.h and emmintrin.h intrinsics. - changed some regular comments '//' into doxygen-style comments '///' where necessary - removed some trailing spaces in doxygen comments. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 298371
* [X86][AVX] Tests showing missing SHUFPD + ZERO loweringSimon Pilgrim2017-03-212-0/+99
| | | | | | This lowers to SHUFPD if the input is zeroinitializer but not with a demanded elts optimized build vector. llvm-svn: 298370
* [OpenCL] Added diagnostic for checking length of vectorEgor Churaev2017-03-213-0/+33
| | | | | | | | | | | | Reviewers: Anastasia, cfe-commits Reviewed By: Anastasia Subscribers: bader, yaxunl Differential Revision: https://reviews.llvm.org/D30937 llvm-svn: 298369
* [AMDGPU] Iterative scheduling infrastructure + minimal registry schedulerValery Pykhtin2017-03-2112-3/+1764
| | | | | | Differential revision: https://reviews.llvm.org/D31046 llvm-svn: 298368
* [GlobalISel] Fix shufflevector testsVolkan Keles2017-03-212-42/+42
| | | | | | | | clang-lld-x86_64-2stage fails because of the order of the instructions. `CHECK-DAG` directives should fix the problem. llvm-svn: 298367
* [OpenCL] Added implicit conversion rank for overloading functions with ↵Egor Churaev2017-03-214-30/+48
| | | | | | | | | | | | | | | | vector data type in OpenCL Summary: I added a new rank to ImplicitConversionRank enum to resolve the function overload ambiguity with vector types. Rank of scalar types conversion is lower than vector splat. So, we can choose which function should we call. See test for more details. Reviewers: Anastasia, cfe-commits Reviewed By: Anastasia Subscribers: bader, yaxunl Differential Revision: https://reviews.llvm.org/D30816 llvm-svn: 298366
* [ADMGPU] SDWA peephole optimization pass.Sam Kolton2017-03-218-1/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: First iteration of SDWA peephole. This pass tries to combine several instruction into one SDWA instruction. E.g. it converts: ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1 V_ADD_I32_e32 %vreg2, %vreg0, %vreg3 V_LSHLREV_B32_e32 %vreg4, 16, %vreg2 ''' Into: ''' V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ''' Pass structure: 1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''. 2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0''' 3. Iterate over all potential instructions and check if they can be converted into SDWA. 4. Convert instructions to SDWA. This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done). There are several ways this pass can be improved: 1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass. 2. Introduce more SDWA patterns 3. Introduce mnemonics to limit when SDWA patterns should apply Reviewers: vpykhtin, alex-t, arsenm, rampitec Subscribers: wdng, nhaehnle, mgorny Differential Revision: https://reviews.llvm.org/D30038 llvm-svn: 298365
* [X86][AVX512] Add _mm512_cvtsd_f64 and _mm512_cvtss_f32 intrinsics (PR32305)Simon Pilgrim2017-03-212-0/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D31155 llvm-svn: 298364
* [change-namespace] avoid adding leading '::' when possible.Eric Liu2017-03-212-62/+124
| | | | | | | | | | | | | | | | | | | | Summary: When changing namespaces, the tool adds leading "::" to references that need to be fully-qualified, which would affect readability. We avoid adding "::" when the symbol name does not conflict with the new namespace name. For example, a symbol name "na::nb::X" conflicts with "ns::na" since it would be resolved to "ns::na::nb::X" in the new namespace. Reviewers: hokein Reviewed By: hokein Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D30493 llvm-svn: 298363
* Stride in distribute parallel for loops with no chunk size.Andrey Churbanov2017-03-211-0/+1
| | | | | | | | Patch by George Rokos. Differential Revision: https://reviews.llvm.org/D24486 llvm-svn: 298362
* [DependenceInfo] change name Write to MustWrite to remove ambiguity [NFC]Siddharth Bhat2017-03-211-13/+15
| | | | | | | | | | | | | | | "Write" is an overloaded term. In collectInfo() till buildFlow(), it is used to mean "must writes". However, within the memory based analysis, it is used to mean "both may and must writes". Renaming the Write variable helps clarify this difference. Reviewers: grosser Tags: #polly Differential Revision: https://reviews.llvm.org/D31181 llvm-svn: 298361
* [DebugInfo][X86] Teach Optimize LEAs pass to handle debug valuesAndrea Di Biagio2017-03-212-7/+133
| | | | | | | | | | | | | | | | This patch fixes an issue in the Optimize LEAs pass where redundant LEAs were not removed because they were being used by debug values. The debug values are now ignored when determining whether LEAs are redundant. For now the debug values for the redundant LEAs are marked as undefined, effectively lost. The intention is for a follow up patch which will attempt to preserve the debug values where possible. Patch by Andrew Ng. Differential Revision: https://reviews.llvm.org/D30835 llvm-svn: 298360
* NFC. InstCombiner::visitFAdd extract LHSIntVal/RHSIntVal local variablesArtur Pilipenko2017-03-211-9/+11
| | | | llvm-svn: 298359
* [GlobalISel] Move isTriviallyDead to Utils. NFC.Volkan Keles2017-03-213-23/+25
| | | | | | Make it accessible by the targets to avoid code duplication. llvm-svn: 298358
* [DAGTypeLegalizer] Handle widening truncate to vector of i1.Jonas Paulsson2017-03-212-1/+58
| | | | | | | | | | | | Previously, PromoteIntRes_TRUNCATE() did not handle the case where the operand needs widening, which resulted in llvm_unreachable(). This patch adds the needed handling, along with a test case. Review: Eli Friedman, Simon Pilgrim. https://reviews.llvm.org/D31077 llvm-svn: 298357
* [ConstantFolding] Fix to prevent constant folding having to repeatedly scan ↵David Green2017-03-212-1/+74
| | | | | | | | | | | | | operands. NFCI After the loop unroll threshold was increased in r295538, very large constant expressions can be created. This prevents them from having to be recursively scanned, leading to a compile time blow-up. Differential Revision: https://reviews.llvm.org/D30689 llvm-svn: 298356
* [scan-build-py] reuse command line output parameter for report directoryLaszlo Nagy2017-03-212-28/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D30861 llvm-svn: 298355
* [ELF] - Detemplate InputSection::getRelocatedSection(). NFC.George Rimar2017-03-213-10/+5
| | | | llvm-svn: 298353
* Update isl to isl-0.18-395-g77701b3Tobias Grosser2017-03-2114-17/+81
| | | | | | This is a normal maintenance update. llvm-svn: 298352
* [ELF] - Detemplate InputSectionBase::uncompress(). NFCGeorge Rimar2017-03-213-10/+4
| | | | llvm-svn: 298351
* [ELF] - Detemplate ARMExidxSentinelSection. NFC.George Rimar2017-03-213-12/+5
| | | | llvm-svn: 298350
* [ELF] - Fix one more access to Sections member.George Rimar2017-03-211-1/+1
| | | | | | That finally should linux BB after r298345. llvm-svn: 298349
* [ELF] Follow-up to r298345 "[ELF] - Detemplate GdbIndexSection."George Rimar2017-03-212-16/+17
| | | | | | | Fix for linux build bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/8144/steps/build/logs/stdio llvm-svn: 298348
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