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* [PPC64LE] Generate correct code for unaligned little-endian vector loadsBill Schmidt2014-06-092-22/+48
| | | | | | | | | | | | | | | | | | | The code in PPCTargetLowering::PerformDAGCombine() that handles unaligned Altivec vector loads generates a lvsl followed by a vperm. As we've seen in numerous other places, the vperm instruction has a big-endian bias, and this is fixed for little endian by complementing the permute control vector and swapping the input operands. In this case the lvsl is providing the permute control vector. Rather than generating an lvsl and a complement operation, it is sufficient to generate an lvsr instruction instead. Thus for LE code generation we will generate an lvsr rather than an lvsl, and swap the other input arguments on the vperm. The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test the code generation for PPC64 and PPC64LE, in addition to the existing PPC32/G5 testing. llvm-svn: 210493
* Generate better location ranges for some register-described variables.Alexey Samsonov2014-06-095-73/+475
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't terminate location ranges for register-described variables at the end of machine basic block if this register is never modified in the function body, except for the prologue and epilogue. Prologue location is guessed by FrameSetup flags on MachineInstructions, while epilogue location is deduced from debug locations of instructions in the basic blocks ending with return instructions. This patch is mostly targeted to fix non-trivial debug locations for variables addressed via stack and frame pointers. It is not really a generic fix. We can still produce poor debug info for register-described variables if this register *is* modified somewhere in the function, but in unrelated places. This might be the case for the debug info in optimized binaries (e.g. for local variables in inlined functions). LiveDebugVariables pass in CodeGen attempts to fix this problem by adjusting DBG_VALUE instructions, but this pass is tied to greedy register allocator, which is used in optimized builds only. Proper fix would likely involve generalizing LiveDebugVariables to all register allocators. See more discussion in http://reviews.llvm.org/D3933 review thread. I'm proceeding with this patch to fix immediate severe problems and important cases, e.g. fix completely broken debug info with AddressSanitizer and fix PR19307 (missing debug info for by-value std::string arguments). llvm-svn: 210492
* Objective-C. Consider block pointer as NSObject as well as conforming toFariborz Jahanian2014-06-092-2/+54
| | | | | | | 'NSCopying' protocol when diagnosing block to ObjC pointer conversion. // rdar://16739120 llvm-svn: 210491
* Update langref for unnamed_addr being allowed in aliases.Rafael Espindola2014-06-091-2/+2
| | | | | | Thanks to Duncan P. N. Exon Smith and Owen Anderson for noticing. llvm-svn: 210490
* ARM: add VLA extension for WoA Itanium ABISaleem Abdulrasool2014-06-095-1/+170
| | | | | | | | | | | | | | | | The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It has a few divergences, mostly revolving around the use of the Itanium ABI for C++. VLA support is one of the extensions that are amongst the set of the extensions. This adds support for proper VLA emission for this environment. This is somewhat similar to the handling for __chkstk emission on X86 and the large stack frame emission for ARM. The invocation style for chkstk is still controlled via the -mcmodel flag to clang. Make an explicit note that this is an extension. llvm-svn: 210489
* Look through addrspacecasts when turning ptr comparisons intoMatt Arsenault2014-06-092-7/+65
| | | | | | index comparisons. llvm-svn: 210488
* Disallow multiple inclusion of clang/Config/config.hAlp Toker2014-06-092-2/+10
| | | | | | Internal config.h headers are only meant to be included from the main file. llvm-svn: 210487
* Added functions cross-reference test.Stepan Dyatkovskiy2014-06-091-0/+27
| | | | | | | | | | | Originally this similar was initiated by Björn Steinbrink here: http://reviews.llvm.org/D3437 Bug itself has been fixed by principal changes in MergeFunctions. Though special checks for functions merging are still actual. And the test has been accepted with slight modifications. llvm-svn: 210486
* Remove old fenv.h workaround for a historic clang driver bugAlp Toker2014-06-091-9/+2
| | | | | | | | | | | Tested and works fine with clang using libstdc++. All indications are that this was fixed some time ago and isn't a problem with any clang version we support. I've added a note in PR6907 which is still open for some reason. llvm-svn: 210485
* Allow definition of dllimport static fields in partial specializations (PR19956)Hans Wennborg2014-06-092-3/+15
| | | | | | This expands the logic from r210141 to cover partial specializations too. llvm-svn: 210484
* Fold FEnv.h into the implementationAlp Toker2014-06-092-63/+41
| | | | | | | | | | | | | | | | | | Support headers shouldn't use config.h definitions, and they should never be undefined like this. ConstantFolding.cpp was the only user of this facility and already includes config.h for other math features, so it makes sense to move the checks there at point of use. (The implicit config.h was also quite dangerous -- removing the FEnv.h include would have silently disabled math constant folding without causing any tests to fail. Need to investigate -Wundef once the cleanup is done.) This eliminates the last config.h include from LLVM headers, paving the way for more consistent configuration checks. llvm-svn: 210483
* [OCaml] Add more Llvm_target testsPeter Zotov2014-06-091-2/+3
| | | | | | Patch by Jacques-Pascal Deplaix llvm-svn: 210482
* Added gdb-remote test for s packet, single stepping.Todd Fiala2014-06-092-22/+220
| | | | llvm-svn: 210481
* [OCaml] Unbreak Llvm_target.TargetMachine.set_verbose_asmPeter Zotov2014-06-091-2/+2
| | | | | | Patch by Jacques-Pascal Deplaix llvm-svn: 210480
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-097-67/+95
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-092-4/+4
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* [X86] Add target combine rules for horizontal add/sub.Andrea Di Biagio2014-06-093-0/+482
| | | | | | | | | | | | | | | | | | | | This patch adds new target specific combine rules to identify horizontal add/sub idioms from BUILD_VECTOR dag nodes. This patch also teaches the DAGCombiner how to canonicalize sequences of insert_vector_elt dag nodes according to the following rule: (insert_vector_elt (insert_vector_elt A, I0), I1) -> (insert_vecto_elt (insert_vector_elt A, I1), I0) This new canonicalization rule only triggers if the inner insert_vector dag node has exactly one use; also, both indices must be known constants, and I1 < I0. This last rule made it possible to write a simpler algorithm to identify horizontal add/sub patterns because now we don't have to worry about the ordering of insert_vector_elt dag nodes. llvm-svn: 210477
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-095-11/+110
| | | | llvm-svn: 210476
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-092-0/+51
| | | | llvm-svn: 210475
* [PPC64LE] Generate correct little-endian code for v16i8 multiplyBill Schmidt2014-06-092-4/+33
| | | | | | | | | | | | | | | | The existing code in PPCTargetLowering::LowerMUL() for multiplying two v16i8 values assumes that vector elements are numbered in big-endian order. For little-endian targets, the vector element numbering is reversed, but the vmuleub, vmuloub, and vperm instructions still assume big-endian numbering. To account for this, we must adjust the permute control vector and reverse the order of the input registers on the vperm instruction. The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed on powerpc64 and powerpc64le targets as well as the original powerpc (32-bit) target. llvm-svn: 210474
* Fix test in r210472.Evgeniy Stepanov2014-06-091-1/+1
| | | | llvm-svn: 210473
* [msan] Workaround for invalid origins in shufflevector.Evgeniy Stepanov2014-06-092-4/+27
| | | | | | | | | Makes origin propagation ignore literal undef operands, and, in general, any operand we don't have origin for. https://code.google.com/p/memory-sanitizer/issues/detail?id=56 llvm-svn: 210472
* llvm/test/CodeGen/X86/2014-05-29-factorial.ll: Relax an expression to match ↵NAKAMURA Takumi2014-06-091-2/+2
| | | | | | Win32 x64. llvm-svn: 210471
* [mips] Fix a bug for NaCl target - Don't report the error when non-dangerousSasa Stankovic2014-06-092-7/+40
| | | | | | | | load/store is in branch delay slot. Differential Revision: http://llvm-reviews.chandlerc.com/D4048 llvm-svn: 210470
* [Mips] Make dt-textrel.test test case independent from external input files.Simon Atanasyan2014-06-091-5/+32
| | | | llvm-svn: 210469
* [X86] Avoid emitting unnecessary test instructions.Andrea Di Biagio2014-06-092-2/+43
| | | | | | | | | | | | | This patch teaches the backend how to check for the 'NoSignedWrap' flag on binary operations to improve the emission of 'test' instructions. If the result of a binary operation is known not to overflow we know that resetting the Overflow flag is unnecessary and so we can avoid emitting the test instruction. Patch by Marcello Maggioni. llvm-svn: 210468
* [DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.Andrea Di Biagio2014-06-097-26/+192
| | | | | | | | | | | | | This patch modifies SelectionDAGBuilder to construct SDNodes with associated NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator instructions. Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing nsw/nuw/exact flags during codegen. Patch by Marcello Maggioni. llvm-svn: 210467
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-096-15/+37
| | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
* [asan] Remove dependency of tests on runtime library in standalone build.Evgeniy Stepanov2014-06-091-2/+4
| | | | llvm-svn: 210465
* [AArch64] Missing aliases for CMP/CMN [W]SP with no shiftArtyom Skrobov2014-06-093-4/+12
| | | | llvm-svn: 210464
* [msan] Intercept __strto*_internal.Evgeniy Stepanov2014-06-092-24/+44
| | | | | | | This should fix strtoimax/strtoumax on newer glibc. https://code.google.com/p/memory-sanitizer/issues/detail?id=36 llvm-svn: 210463
* [docs] Fix typo, align comments, fix syntax highlightingJeroen Ketema2014-06-091-17/+17
| | | | llvm-svn: 210462
* Remove dead parameter.Rui Ueyama2014-06-091-3/+3
| | | | llvm-svn: 210461
* [mips][mips64r6] Add LDPC instructionZoran Jovanovic2014-06-0910-6/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
* Fix line numbers for code inlined from __nodebug__ functions.Evgeniy Stepanov2014-06-095-4/+91
| | | | | | | | | | | | | | Instructions from __nodebug__ functions don't have file:line information even when inlined into no-nodebug functions. As a result, intrinsics (SSE and other) from <*intrin.h> clang headers _never_ have file:line information. With this change, an instruction without !dbg metadata gets one from the call instruction when inlined. Fixes PR19001. llvm-svn: 210459
* [msan] Add a test for mmx.packuswb.Evgeniy Stepanov2014-06-091-0/+22
| | | | llvm-svn: 210458
* [msan] Simplify tests.Evgeniy Stepanov2014-06-091-18/+25
| | | | llvm-svn: 210457
* Re-commit r210425.Rui Ueyama2014-06-092-3/+78
| | | | llvm-svn: 210456
* Add missing dependency for check-lld.Rui Ueyama2014-06-091-1/+1
| | | | llvm-svn: 210455
* [msan] Fix vector pack intrinsic handling.Evgeniy Stepanov2014-06-092-9/+95
| | | | | | | | | This fixes a crash on MMX intrinsics, as well as a corner case in handling of all unsigned pack intrinsics. PR19953. llvm-svn: 210454
* R600: Add more and testcasesMatt Arsenault2014-06-091-18/+88
| | | | llvm-svn: 210453
* [asan] Add malloc_usable_size to android malloc dispatch.Evgeniy Stepanov2014-06-091-8/+10
| | | | llvm-svn: 210452
* Revert "[Mips] Make got16.test test case independent from external input files."Rui Ueyama2014-06-092-78/+3
| | | | | | | This reverts commit r210425 because the test added in the commit is broken. llvm-svn: 210451
* Fix gcc warning (enumeral and non-enumeral type in conditional expression)Patrik Hagglund2014-06-091-1/+2
| | | | llvm-svn: 210450
* [PPC64LE] Implement little-endian semantics for vec_sumsBill Schmidt2014-06-092-0/+30
| | | | | | | | | | | | | | | | | | The PowerPC vsumsws instruction, accessed via vec_sums, is defined architecturally with a big-endian bias, in that the second input vector and the result always reference big-endian element 3 (little-endian element 0). For ease of porting, the programmer wants elements 3 in both cases. To provide this semantics, for little endian we generate a permute for the second input vector prior to the vsumsws instruction, and generate a permute for the result vector following the vsumsws instruction. The correctness of this code is tested by the new sums.c test added in a previous patch, as well as the modifications to builtins-ppc-altivec.c in the present patch. llvm-svn: 210449
* [C++11] Use 'nullptr'.Craig Topper2014-06-0910-27/+30
| | | | llvm-svn: 210448
* [C++11] Use 'nullptr'.Craig Topper2014-06-0922-73/+74
| | | | llvm-svn: 210447
* [AArch64] Fix the ordering of the accumulate operand in SchedRW list.Chad Rosier2014-06-092-6/+7
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 llvm-svn: 210446
* [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shiftChad Rosier2014-06-092-9/+17
| | | | | | | plus add. The shift can be folded into the add. This only effects codegen when the constant is 3. llvm-svn: 210445
* [SeparateConstOffsetFromGEP] inbounds zext => sext for better splittingJingyue Wu2014-06-083-4/+128
| | | | | | | | | | For each array index that is in the form of zext(a), convert it to sext(a) if we can prove zext(a) <= max signed value of typeof(a). The conversion helps to split zext(x + y) into sext(x) + sext(y). Reviewed in http://reviews.llvm.org/D4060 llvm-svn: 210444
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