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* [cmake] Support host architectures other than x64Shoaib Meenai2017-12-131-5/+28
| | | | | | | | Allow building for other architectures when cross-compiling for Windows. Differential Revision: https://reviews.llvm.org/D41158 llvm-svn: 320656
* Recommit r320461 "[X86] Use regular expressions more aggressively to reduce ↵Craig Topper2017-12-134-1032/+48
| | | | | | | | | | | | | | the number of scheduler entries needed for FMA3 instructions." I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name. Original commit message: When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320655
* Move Repl to SectionBase.Rafael Espindola2017-12-134-25/+18
| | | | | | | | | | | | | | | | It is currently in InputSectionBase. Only InputSections are used in ICF, so Repl should be move to InputSection to clear the class hierarchy or, like this patch does, to SectionBase for convenience. The convenience of having it on the base class is that we can just access the replacement without having to first check if it is an InputSection. It is a bit less code and a bit faster as some of this code is very hot. I got up to 1.77% improvement in clang-gdb-index and no regressions according to lnt. llvm-svn: 320654
* [EarlyCSE] recognize swapped variants of abs/nabs as equivalentSanjay Patel2017-12-132-15/+14
| | | | | | | | Extends https://reviews.llvm.org/rL320640 Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320653
* Inline a small function.Rui Ueyama2017-12-132-11/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D41204 llvm-svn: 320652
* [X86] Add missing MULX32 schedule testSimon Pilgrim2017-12-131-1/+51
| | | | llvm-svn: 320651
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-134-11/+125
| | | | | | | | | | | | | | | | | Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
* [CodeView] Teach clang to emit the .debug$H COFF section.Zachary Turner2017-12-1311-15/+592
| | | | | | | | | | | | | | | Currently this is an LLVM extension to the COFF spec which is experimental and intended to speed up linking. For now it is behind a hidden cl::opt flag, but in the future we can move it to a "real" cc1 flag and have the driver pass it through whenever it is appropriate. The patch to actually make use of this section in lld will come in a followup. Differential Revision: https://reviews.llvm.org/D40917 llvm-svn: 320649
* Recover some overzealously removed includes.Michael Zolotukhin2017-12-135-0/+5
| | | | llvm-svn: 320648
* [EarlyCSE] add tests for swapped abs/nabs; NFCSanjay Patel2017-12-131-0/+38
| | | | llvm-svn: 320647
* Speculative build fix for llvm-pdbdump on Linux after Michael's #include ↵Hans Wennborg2017-12-131-0/+1
| | | | | | removals llvm-svn: 320646
* Speculative build fix for lld on Linux after Michael's #include removalsHans Wennborg2017-12-131-0/+1
| | | | llvm-svn: 320645
* [X86] Add CLWB schedule testSimon Pilgrim2017-12-131-0/+18
| | | | llvm-svn: 320644
* [libFuzzer] Add dummy call of LLVMFuzzerTestOneInput to afl_driver.Matt Morehouse2017-12-131-1/+7
| | | | | | | | | | | | | | | | | | | | Summary: Add dummy call of LLVMFuzzerTestOneInput to afl_driver before it starts executing on actual inputs. Do this so that first time initialization performed by LLVMFuzzerTestOneInput is not considered code covered by a particular input. Patch By: metzman Reviewers: kcc, morehouse Reviewed By: kcc Subscribers: llvm-commits, Sanitizers Differential Revision: https://reviews.llvm.org/D41193 llvm-svn: 320643
* [WebAssembly] Use bitfield types in wasm YAML representationSam Clegg2017-12-1317-53/+90
| | | | | | Differential Revision: https://reviews.llvm.org/D41202 llvm-svn: 320642
* Reverting [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-1312-893/+99
| | | | | | | Stage 2 bootstrap failed: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434 llvm-svn: 320641
* [EarlyCSE] recognize commuted and swapped variants of min/max as equivalent ↵Sanjay Patel2017-12-132-22/+54
| | | | | | | | | | | | | (PR35642) As shown in: https://bugs.llvm.org/show_bug.cgi?id=35642 ...we can have different forms of min/max, so we should recognize those here in EarlyCSE similar to how we already handle binops and compares that can commute. Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320640
* [WebAssembly] Add linking metatdata test coverage for wasm2yamlSam Clegg2017-12-133-2/+60
| | | | | | | | Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41196 llvm-svn: 320639
* IRGen: When performing CFI checks, load vtable pointer from vbase when ↵Peter Collingbourne2017-12-137-12/+103
| | | | | | | | | | | | | | necessary. Under the Microsoft ABI, it is possible for an object not to have a virtual table pointer of its own if all of its virtual functions were introduced by virtual bases. In that case, we need to load the vtable pointer from one of the virtual bases and perform the type check using its type. Differential Revision: https://reviews.llvm.org/D41036 llvm-svn: 320638
* [X86] Move ADX schedule tests out of schedule-x86_64.llSimon Pilgrim2017-12-132-208/+114
| | | | llvm-svn: 320637
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-1312-31/+0
| | | | llvm-svn: 320636
* Remove redundant includes from lib/Target/ARM.Michael Zolotukhin2017-12-138-17/+0
| | | | llvm-svn: 320635
* Remove redundant includes from lib/Target/AArch64.Michael Zolotukhin2017-12-137-13/+0
| | | | llvm-svn: 320634
* Remove redundant includes from lib/Target/*.cpp.Michael Zolotukhin2017-12-133-5/+0
| | | | llvm-svn: 320633
* Remove redundant includes from utils/TableGen.Michael Zolotukhin2017-12-136-7/+0
| | | | llvm-svn: 320632
* Remove redundant includes from tools.Michael Zolotukhin2017-12-1345-141/+0
| | | | llvm-svn: 320631
* Remove redundant includes from unittests.Michael Zolotukhin2017-12-1317-38/+0
| | | | llvm-svn: 320630
* Remove redundant includes from various places.Michael Zolotukhin2017-12-134-7/+0
| | | | llvm-svn: 320629
* Remove redundant includes from lib/Transforms.Michael Zolotukhin2017-12-1331-48/+0
| | | | llvm-svn: 320628
* Remove redundant includes from lib/Support.Michael Zolotukhin2017-12-136-6/+0
| | | | llvm-svn: 320627
* Remove redundant includes from lib/ProfileData.Michael Zolotukhin2017-12-132-9/+0
| | | | llvm-svn: 320626
* Remove redundant includes from lib/Object.Michael Zolotukhin2017-12-133-13/+0
| | | | llvm-svn: 320625
* Remove redundant includes from lib/MC.Michael Zolotukhin2017-12-1310-19/+0
| | | | llvm-svn: 320624
* Remove redundant includes from lib/LTO.Michael Zolotukhin2017-12-133-9/+0
| | | | llvm-svn: 320623
* Remove redundant includes from lib/IR.Michael Zolotukhin2017-12-1310-12/+1
| | | | llvm-svn: 320622
* Remove redundant includes from lib/ExecutionEngine.Michael Zolotukhin2017-12-133-4/+0
| | | | llvm-svn: 320621
* Remove redundant includes from lib/DebugInfo.Michael Zolotukhin2017-12-1324-33/+0
| | | | llvm-svn: 320620
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-1332-56/+0
| | | | llvm-svn: 320619
* Remove redundant includes from lib/Bitcode.Michael Zolotukhin2017-12-132-5/+0
| | | | llvm-svn: 320618
* Remove redundant includes from lib/Analysis.Michael Zolotukhin2017-12-1312-14/+0
| | | | llvm-svn: 320617
* [cmake] Explicitly set VS 2017 compatibilityShoaib Meenai2017-12-131-0/+1
| | | | | | | | | | | | | When cross-compiling using clang-cl 5.0 (which is currently the latest stable release of the compiler), the default MS compatibility level is set to VS 2013, which is too low to build LLVM. Explicitly set the compatibility level to VS 2017 to support cross-compiling LLVM for Windows using clang-cl 5.0. This will be a no-op when using clang-cl 6.0 and above, where the default MS compatibility level is already VS 2017. Differential Revision: https://reviews.llvm.org/D41157 llvm-svn: 320616
* [cmake] Determine MSVC host triple correctly when cross-compilingShoaib Meenai2017-12-131-1/+1
| | | | | | | | | | | | | | | | CMAKE_CL_64 will never be set when cross-compiling with clang-cl, since CMake relies on an actual VS environment in order to determine it. Instead, use the size of a void pointer to determine the bit width of the host compiler (and therefore the host triple), which works for both native and cross compilation. Note that, with the impending advent of Windows on AArch64, assuming that a 64-bit host == x86_64 isn't correct either, but that's something to be addressed in a follow-up. Differential Revision: https://reviews.llvm.org/D41155 llvm-svn: 320615
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-139-78/+167
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* [OPENMP] Add codegen for `nowait` clause in target directives.Alexey Bataev2017-12-1310-21/+68
| | | | | | Added basic codegen for `nowait` clauses in target-based directives. llvm-svn: 320613
* [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-1312-99/+893
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: See D37528 for a previous (non-deferred) version of this patch and its description. Preserves dominance in a deferred manner using a new class DeferredDominance. This reduces the performance impact of updating the DominatorTree at every edge insertion and deletion. A user may call DDT->flush() within JumpThreading for an up-to-date DT. This patch currently has one flush() at the end of runImpl() to ensure DT is preserved across the pass. LVI is also preserved to help subsequent passes such as CorrelatedValuePropagation. LVI is simpler to maintain and is done immediately (not deferred). The code to perfom the preversation was minimally altered and was simply marked as preserved for the PassManager to be informed. This extends the analysis available to JumpThreading for future enhancements. One example is loop boundary threading. Reviewers: dberlin, kuhar, sebpop Reviewed By: kuhar, sebpop Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40146 llvm-svn: 320612
* [scudo] Adding a public Scudo interfaceKostya Kortchinsky2017-12-136-3/+123
| | | | | | | | | | | | | | | | Summary: The first and only function to start with allows to set the soft or hard RSS limit at runtime. Add associated tests. Reviewers: alekseyshl Reviewed By: alekseyshl Subscribers: mgorny, #sanitizers, llvm-commits Differential Revision: https://reviews.llvm.org/D41128 llvm-svn: 320611
* Add missing reference to lldCommon in MinGW/CMakeLists.txtSam Clegg2017-12-132-1/+1
| | | | | | | | | | | Without this the LLVM_BUILD_LLVM_DYLIB+DLLVM_LINK_LLVM_DYLIB build break. Also remove unneeded lldCore from wasm/CMakeLists.txt Differential Revision: https://reviews.llvm.org/D41194 llvm-svn: 320610
* [Hexagon] Intrinsic support for V62 and V65Krzysztof Parzyszek2017-12-134-1875/+2547
| | | | llvm-svn: 320609
* [OPENMP] Initial codegen for `target teams distribute simd` directive.Alexey Bataev2017-12-1315-17/+2914
| | | | | | | Host + generic device codegen for `target teams distribute simd` directive. llvm-svn: 320608
* [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases loadAditya Kumar2017-12-132-2/+27
| | | | | | | | | | | | | | w.r.t. the paper "A Practical Improvement to the Partial Redundancy Elimination in SSA Form" (https://sites.google.com/site/jongsoopark/home/ssapre.pdf) Proper dominance check was missing here, so having a loopinfo should not be required. Committing this diff as this fixes the bug, if there are further concerns, I'll be happy to work on them. Differential Revision: https://reviews.llvm.org/D39781 llvm-svn: 320607
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