| Commit message (Collapse) | Author | Age | Files | Lines |
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on invalid code and we don't really care, so kill it harder.
llvm-svn: 125068
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integer. Modified patch from Kirk Beitz.
llvm-svn: 125067
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the active loop. This is generally desirable, and it avoids trouble
in situations such as the testcase in PR9123, though the failure
mode depends on use-list order, so it is infeasible to test.
llvm-svn: 125065
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flags such that symbols can be searched for within a shared library if desired.
Platforms that support the RTLD_FIRST flag can still take advantage of their
quicker lookups, and other platforms can still get the same fucntionality
with a little extra work.
Also changed LLDB_CONFIG flags over to either being defined, or not being
defined to stay in line with current open source practices and to prepare for
using autoconf or cmake to configure LLDB builds.
llvm-svn: 125064
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in liu of a class method getter. objc++ uses a different
code path and is more involved (TBD).
llvm-svn: 125061
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in g_thumb_opcodes
as pointed out By Caroline. Refactored a little bit by adding two new helper methods to the
EmulateInstructionARM class:
o BranchWritePC()
o BXWritePC()
llvm-svn: 125059
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After uses of a live range are removed, recompute the live range to only cover
the remaining uses. This is necessary after rematerializing the value before
some (but not all) uses.
llvm-svn: 125058
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where the implementation is hidden in the host layer. This avoids
a slew of "#if LLDB_CONFIG_TERMIOS_SUPPORTED" statements in the
code and keeps things cleaner.
llvm-svn: 125057
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switch. If we used only one icmp, don't turn it into a switch.
Also prevent the switch-to-icmp transform from creating identity adds, noticed by Marius Wachtler.
llvm-svn: 125056
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llvm-svn: 125055
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llvm-svn: 125054
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parsing of operands introduced in r125030. As a small note, besides using a more
generic approach we can also have more descriptive output when debugging
llvm-mc, example:
mcr p7, #1, r5, c1, c1, #4
note: parsed instruction:
['mcr', <ARMCC::al>,
<coprocessor number: 7>,
1,
<register 73>,
<coprocessor register: 1>,
<coprocessor register: 1>,
4]
llvm-svn: 125052
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g_thumb_opcodes
tables. EmulateB() has empty impl. and needs to be filled in later.
llvm-svn: 125048
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llvm-svn: 125047
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llvm-svn: 125031
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Motivation: Improve the parsing of not usual (different from registers or
immediates) operand forms.
This commit implements only the generic support. The ARM specific modifications
will come next.
A table like the one below is autogenerated for every instruction
containing a 'ParserMethod' in its AsmOperandClass
static const OperandMatchEntry OperandMatchTable[20] = {
/* Mnemonic, Operand List Mask, Operand Class, Features */
{ "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 },
{ "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM },
A matcher function very similar (but lot more naive) to
MatchInstructionImpl scans the table. After the mnemonic match, the
features are checked and if the "to be parsed" operand index is
present in the mask, there's a real match. Then, a switch like the one
below dispatch the parsing to the custom method provided in
'ParseMethod':
case MCK_Coproc:
return TryParseCoprocessorOperandName(Operands);
llvm-svn: 125030
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couple of utility functions that will be used in other places for more
AVX lowering.
llvm-svn: 125029
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#include "lldb/Host/Config.h"
Or the LLDB_CONFIG_TERMIOS_SUPPORTED defined won't be set. I will fix all
of this Termios stuff later today by moving lldb/Core/TTYState.* into the
host layer and then we conditionalize all of this inside TTYState.cpp and
then we get rid of LLDB_CONFIG_TERMIOS_SUPPORTED all together.
Typically, when we start to see too many "#if LLDB_CONFIG_XXXX" preprocessor
directives, this is a good indicator that something needs to be moved over to
the host layer. TTYState can be modified to do all of the things that many
areas of the code are currently doing, and it will avoid all of the
preprocessor noise.
llvm-svn: 125027
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llvm-svn: 125025
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llvm-svn: 125024
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llvm-svn: 125023
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llvm-svn: 125021
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llvm-svn: 125019
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llvm-svn: 125016
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avoid using RTLD_FIRST with dlopen to keep things compatible with other *NIX
variants. Patch from Jai Menon.
llvm-svn: 125015
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The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.
llvm-svn: 125014
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These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.
llvm-svn: 125013
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llvm-svn: 125012
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llvm-svn: 125011
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until the instructions are emitted or printed.
llvm-svn: 125010
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llvm-svn: 125009
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that aren't always available (sometimes d_namlen or d_reclen). Now strlen is
used to avoid such issues.
llvm-svn: 125008
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-Wuninitialized-experimental. It is clear from user feedback that this warning is not quite ready.
llvm-svn: 125007
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Factor some code better.
llvm-svn: 125006
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- BlockDeclRefExprs always store VarDecls
- BDREs no longer store copy expressions
- BlockDecls now store a list of captured variables, information about
how they're captured, and a copy expression if necessary
With that in hand, change IR generation to use the captures data in
blocks instead of walking the block independently.
Additionally, optimize block layout by emitting fields in descending
alignment order, with a heuristic for filling in words when alignment
of the end of the block header is insufficient for the most aligned
field.
llvm-svn: 125005
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to simplify the "(X/Y)*Y->X when the division is exact" transform.
llvm-svn: 125004
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llvm-svn: 125002
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Fixes PR9159.
llvm-svn: 125001
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llvm-svn: 125000
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failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
llvm-svn: 124996
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Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.
llvm-svn: 124995
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when the div is an exact udiv.
llvm-svn: 124994
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llvm-svn: 124993
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instcombine xform to exercise this.
Nothing forms exact udivs yet though. This is progress on PR8862
llvm-svn: 124992
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if we weren't going to inline the function. The rest of the code using
this was removed.
Fixes PR9154.
llvm-svn: 124991
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llvm-svn: 124990
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llvm-svn: 124989
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llvm-svn: 124988
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resulting pointer type both have the same size.
llvm-svn: 124987
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linkage, we should change its linkage instead of asserting.
llvm-svn: 124986
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