summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* [PPC64][test] Delete redundant labels from ppc64-relocs.sFangrui Song2019-05-311-80/+20
| | | | llvm-svn: 362235
* [NFC][InstCombine] Add unary FNeg tests to fcmp.llCameron McInally2019-05-311-0/+118
| | | | llvm-svn: 362234
* [MachinePipeliner][NFC] Add some debug log and statisticsJinsong Ji2019-05-311-12/+71
| | | | | | | | This is to add some log and statistics for debugging Differential Revision: https://reviews.llvm.org/D62165 llvm-svn: 362233
* Revise test case due to the change from CUDA 10+.Michael Liao2019-05-311-1/+1
| | | | llvm-svn: 362232
* [NFC][InstCombine] Add unary FNeg tests to fdiv.llCameron McInally2019-05-311-0/+118
| | | | llvm-svn: 362231
* [AMDGPU] Regenerate add/sub shrink constant tests for an upcoming patchSimon Pilgrim2019-05-311-45/+390
| | | | llvm-svn: 362230
* [AMDGPU] Regenerate CTLZ tests for an upcoming patchSimon Pilgrim2019-05-311-128/+1006
| | | | llvm-svn: 362229
* [UpdateTestChecks] Add support for -march=r600 to match existing ↵Simon Pilgrim2019-05-311-0/+1
| | | | | | -march=amdgcn support llvm-svn: 362228
* [NFC][InstCombine] Add unary FNeg tests to fma.llCameron McInally2019-05-311-0/+96
| | | | llvm-svn: 362227
* [clangd] Add missing license for rename.cpp, NFC.Haojian Wu2019-05-311-1/+9
| | | | llvm-svn: 362226
* Fix for PR42089, regression from r362119Erich Keane2019-05-312-1/+17
| | | | | | | | | The implementation of the NoThrow ExceptionSpecificationType missed a switch statement for forming the diagnostic when an out-of-line member redeclaration misses the exception specification. This patch adds the correct case statement. llvm-svn: 362225
* [llvm-readobj] - Remove excessive `dynamic.test`George Rimar2019-05-313-248/+0
| | | | | | | | | | | | | | | | | | | | | | | | | dynamic.test is a test that checks dumping of dynamic tags. It uses precompiled objects as inputs and it is completely excessive nowadays: Now we have elf-dynamic-tags-machine-specific.test and elf-dynamic-tags.test. (https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags-machine-specific.test) (https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags.test) First is used to check target specific tags and second tests the common flags. These tests use YAML, which is much better than using precompiled binaries. Note that new reviews tend to update the YAML based tests to add new tags, e.g. see D62596. With this patch it became possible to remove dynamic-table-so.aarch64 binary from the inputs folder. (other binaries are still used in other tests). Differential revision: https://reviews.llvm.org/D62728 llvm-svn: 362224
* gn build: Merge r362160Nico Weber2019-05-311-0/+1
| | | | llvm-svn: 362223
* gn build: Merge r362196Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362222
* gn build: Merge r362190Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362221
* [ELF] Delete GotEntrySize and GotPltEntrySizeFangrui Song2019-05-3112-35/+14
| | | | | | | | | | | | | GotEntrySize and GotPltEntrySize were added in D22288. Later, with the introduction of wordsize() (then Config->Wordsize), they become redundant, because there is no target that sets GotEntrySize or GotPltEntrySize to a number different from Config->Wordsize. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D62727 llvm-svn: 362220
* ftime-trace: Trace loop passesRussell Gallop2019-05-311-0/+3
| | | | | | | | | | These can take a significant amount of time in some builds. Suggested by Andrea Di Biagio. Differential Revision: https://reviews.llvm.org/D62666 llvm-svn: 362219
* [ELF] Replace a dead test in getSymVA() with assert()Fangrui Song2019-05-311-7/+1
| | | | | | | | | | | | Symbols relative to discarded comdat sections are Undefined instead of Defined now (after D59649 and D61583). The `== &InputSection::Discarded` test becomes dead. I cannot find a test related to this behavior. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62725 llvm-svn: 362218
* [InstCombine] 'C-(C2-X) --> X+(C-C2)' constant-foldRoman Lebedev2019-05-312-3/+8
| | | | | | | | | | It looks this fold was already partially happening, indirectly via some other folds, but with one-use limitation. No other fold here has that restriction. https://rise4fun.com/Alive/ftR llvm-svn: 362217
* [InstCombine] 'add (sub C1, X), C2 --> sub (add C1, C2), X' constant-foldRoman Lebedev2019-05-312-19/+18
| | | | | | https://rise4fun.com/Alive/qJQ llvm-svn: 362216
* [AArch64][SVE2] Asm: support WHILE instructionsCullen Rhodes2019-05-3114-0/+543
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62601 llvm-svn: 362215
* [AArch64][SVE2] Asm: support TBL/TBX instructionsCullen Rhodes2019-05-316-7/+181
| | | | | | | | | | | | | | | | | Summary: A three sources variant of the TBL instruction is added to the existing SVE instruction in SVE2. This is implemented with minor changes to the existing TableGen class. TBX is a new instruction with its own definition. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62600 llvm-svn: 362214
* [AArch64][SVE2] Asm: support SVE2 store instructionsCullen Rhodes2019-05-3111-2/+661
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * STNT1B, STNT1H, STNT1S, STNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62599 llvm-svn: 362213
* [MIPS GlobalISel] Add detailed tests for lower callPetar Avramovic2019-05-312-5/+298
| | | | | | | | | | | | | | | | Test different operand types of callee and their behavior whether relocation model is pic or not. Possible operand types are: Register (function pointer), External symbol (used for libcalls e.g. __udivdi3 or memcpy), Global address. Global address has different handling depending on relocation model and linkage type. Register and external symbol do not. Differential Revision: https://reviews.llvm.org/D62590 llvm-svn: 362212
* Follow up and fix for rL362064Sjoerd Meijer2019-05-311-1/+2
| | | | | | | | Fix the misleadingly indentation introduced in rL362064. This will get rid of the compiler warning, and it was actually a bug. This change will be used and tested in D62669. llvm-svn: 362211
* [MIPS GlobalISel] Handle position independent code Petar Avramovic2019-05-319-19/+451
| | | | | | | | | | | | | Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
* [NFC][InstCombine] Copy add/sub constant-folding tests from codegenRoman Lebedev2019-05-311-0/+536
| | | | | | Last three patterns are missed. llvm-svn: 362209
* [NFC][Codegen] Add/sub constant-folding: add scalar tests tooRoman Lebedev2019-05-312-182/+953
| | | | | | Just for completeness. llvm-svn: 362208
* [ELF][test] Restore linkerscript/symbol-location.s to test ↵Fangrui Song2019-05-311-0/+16
| | | | | | | | | | | | getLinkerScriptLocation() The test (the only test that checks getLinkerScriptLocation()) deleted by r358652 can be restored by replacing R_X86_64_PLT32 with R_X86_64_PC32, and changing -pie to -shared (preemptable). Then, the symbol will not be a link-time constant and a -fPIC error will be issued. llvm-svn: 362207
* [mips] Move initGlobalBaseReg to MipsFunctionInfo. NFCPetar Avramovic2019-05-314-94/+93
| | | | | | | | | | | Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
* [InstructionSimplify] Add missing implementation of llvm::SimplifyUnOp. NFCCraig Topper2019-05-311-0/+4
| | | | | | | There are no callers currently, but the function is declared so we should at least implement it. llvm-svn: 362205
* [MIPS GlobalISel] Lower call for callee that is registerPetar Avramovic2019-05-312-6/+28
| | | | | | | | | Lower call for callee that is register for MIPS32. Register should contain callee function address. Differential Revision: https://reviews.llvm.org/D62585 llvm-svn: 362204
* [X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.Craig Topper2019-05-316-77/+36
| | | | | | | | | | | | | | These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits. Similar to PR42079. Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the load pattern used in the instructions. This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe we should use VZMOVL for widened loads even when we don't need the upper bits as zeroes? llvm-svn: 362203
* [X86] Add test cases for failure to use 128-bit masked vcvtdq2pd when load ↵Craig Topper2019-05-312-0/+212
| | | | | | starts as v2i32. llvm-svn: 362202
* [X86] Add test cases for a volatile load shrinking bug involving cvtdq2pd. NFCCraig Topper2019-05-312-276/+308
| | | | | | Similar to PR42079 llvm-svn: 362201
* [X86] Copy a test case from avx512-cvt.ll to avx512-cvt-widen.ll. NFCCraig Topper2019-05-311-0/+23
| | | | llvm-svn: 362200
* [X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp ↵Craig Topper2019-05-313-16/+62
| | | | | | | | | | | | | | | | | extloads instead. DAG combine will usually fold fpextend+load to an fp extload anyway. So the 256 and 512 patterns were probably unnecessary. The 128 bit pattern was special in that it looked for a v4f32 load, but then used it in an instruction that only loads 64-bits. This is bad if the load happens to be volatile. We could probably make the patterns volatile aware, but that's more work for something that's probably rare. The peephole pass might kick in and save us anyway. We might also be able to fix this with some additional DAG combines. This also adds patterns for vselect+extload to enabled masked vcvtps2pd to be used. Previously we looked for the unlikely vselect+fpextend+load. llvm-svn: 362199
* [X86] Add test to show missed opportunity to use masked vcvtps2pd for ↵Craig Topper2019-05-311-0/+24
| | | | | | vselect+extload. llvm-svn: 362198
* [X86] Add test case for PR42079. NFCCraig Topper2019-05-311-0/+45
| | | | llvm-svn: 362197
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-3115-3/+343
| | | | | | | | | | Support intel AVX512 VP2INTERSECT instructions in clang Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62367 llvm-svn: 362196
* [MIR-Canon] Skip the first N vreg names lazily.Puyan Lotfi2019-05-312-9/+10
| | | | | | | | | | | | | | | This consolidates the vreg skip code into one function (SkipVRegs()). SkipVRegs() now knows if it should skip as if it is the first initialization or subsequent skips. The first skip is also done the first time createVirtualRegister is called by the cursor instead of by the cursor's constructor. This prevents verifier errors on machine functions that have no vregs (where the verifier will complain that there are vregs when the function uses none). Differential Revision: https://reviews.llvm.org/D62717 llvm-svn: 362195
* Fix problem with r362192Richard Trieu2019-05-311-5/+8
| | | | | | | The string returned only sometimes ends in NULL. Explicitly check for the NULL and pop off the NULL if it is there. llvm-svn: 362194
* [X86] Correct the ins operand order for MASKPAIR16STORE to match other store ↵Craig Topper2019-05-312-6/+6
| | | | | | | | | | | | | | | | | | instructions. This makes the 5 address operands come first. And the data operand comes last. This matches the operand order the instruction is created with. It's also the expected order in X86MCInstLower. So everything appeared to work, but the operands didn't match their declared type. Fixes a -verify-machineinstrs failure. Also remove the isel patterns from these instructions since they should only be used for stack spills and reloads. I'm not even sure what types the patterns were looking for to match. llvm-svn: 362193
* Fix off-by-one error.Richard Trieu2019-05-311-1/+1
| | | | | | | The created string is one char too large, so it pulls the terminating NULL as the last character of the string. This later causes SocketTest.cpp to fail. llvm-svn: 362192
* [MIR-Canon] Hardening propagateLocalCopies.Puyan Lotfi2019-05-312-6/+19
| | | | | | | | | | This is am almost NFC, it does the following: - If there is no register class for a COPY's src or dst, bail. - Fixes uses iterator invalidation bug. Differential Revision: https://reviews.llvm.org/D62713 llvm-svn: 362191
* re-commit r361928: [PowerPC] [Clang] Port SSE intrinsics to PowerPCZi Xuan Wu2019-05-3110-17/+4160
| | | | | | | | | | | | | | | Port xmmintrin.h which include Intel SSE intrinsics implementation to PowerPC platform (using Altivec). The new headers containing those implemenations are located into a directory named ppc_wrappers which has higher priority when the platform is PowerPC on Linux. They are mainly developed by Steven Munroe, with contributions from Paul Clarke, Bill Schmidt, Jinsong Ji and Zixuan Wu. Patched by: Qiu Chaofan <qiucf@cn.ibm.com> Reviewed By: Jinsong Ji Differential Revision: https://reviews.llvm.org/D62121 llvm-svn: 362190
* Fix bad go bindings test.Richard Trieu2019-05-311-1/+0
| | | | | | | After r362128, the "byval" attribute has a stricter check and will cause an assertion. Remove the "byval" test case for now. llvm-svn: 362189
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-3139-1/+2816
| | | | | | | | | | Support Intel AVX512 VP2INTERSECT instructions in llvm Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62366 llvm-svn: 362188
* Redirect test output to /dev/nullRichard Trieu2019-05-311-5/+5
| | | | llvm-svn: 362187
* Revert "[X86] Fix i386 struct and union parameter alignment"Pengfei Wang2019-05-313-48/+14
| | | | | | | | | | This reverts commit d61cb749f4ac2c90244906d756e80a5c4a7ffa89 (SVN: 361934). According to James suggestion, revert this change. Please ref: https://reviews.llvm.org/D60748 llvm-svn: 362186
OpenPOWER on IntegriCloud