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* [hwasan] Rename sized load/store callbacks to be consistent with ASan.Evgeniy Stepanov2018-01-163-11/+11
| | | | | | | | | | | | Summary: __hwasan_load is now __hwasan_loadN. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D42138 llvm-svn: 322601
* [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructionsSimon Pilgrim2018-01-163-6/+6
| | | | | | For some reason they don't have a trailing i like the packed equivalents. llvm-svn: 322600
* [CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.Florian Hahn2018-01-165-168/+163
| | | | | | | | | | | | | | | This removes some duplication from splitCallSite and makes it easier to add additional code dealing with each predecessor. It also allows us to split for more than 2 predecessors, although that is not enabled for now. Reviewers: junbuml, mcrosier, davidxl, davide Reviewed By: junbuml Differential Revision: https://reviews.llvm.org/D41858 llvm-svn: 322599
* [X86][BTVER2] Use instrs instead of instregex for low match counts (PR35955)Simon Pilgrim2018-01-161-30/+22
| | | | llvm-svn: 322598
* [X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)Simon Pilgrim2018-01-161-36/+33
| | | | llvm-svn: 322597
* [PPC64] Added vector registers.Martin Storsjo2018-01-167-360/+807
| | | | | | | | | | | | | | | | The Registers_ppc64 class needed a couple of changes, both to accommodate the new registers as well as to handle the overlaps of VS register set without wasting space. The save/restore code of V and VS registers was added. As VS registers depend on the VMX extension, they are processed only if VMX support is detected (_ARCH_PWR8 for now). Patch by Leandro Lupori! Differential Revision: https://reviews.llvm.org/D41906 llvm-svn: 322596
* Specify inline for isWhitespace in CommandLine.cppRui Ueyama2018-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Takuto Ikuta. In chromium's component build, there are many directive sections and commandline parsing takes much time. This patch is for speed up of lld in RelWithDebInfo build by forcing inline heavily called isWhitespace function. 10 times link perf stats of blink_core.dll changed like below. master: TotalSeconds: 9.8764878 TotalSeconds: 10.1455242 TotalSeconds: 10.075279 TotalSeconds: 10.3397347 TotalSeconds: 9.8361665 TotalSeconds: 9.9544441 TotalSeconds: 9.8960686 TotalSeconds: 9.8877865 TotalSeconds: 10.0551879 TotalSeconds: 10.0492254 Avg: 10.01159047 with this patch: TotalSeconds: 8.8696762 TotalSeconds: 9.1021585 TotalSeconds: 9.0233893 TotalSeconds: 9.1886175 TotalSeconds: 9.156954 TotalSeconds: 9.0978564 TotalSeconds: 9.1316824 TotalSeconds: 8.8354606 TotalSeconds: 9.2549431 TotalSeconds: 9.4473085 Avg: 9.11080465 llvm-svn: 322595
* [ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.Lang Hames2018-01-163-5/+5
| | | | | | For symmetry with isWeak, isCommon. llvm-svn: 322594
* Add context to why test was disabled on WindowsRichard Trieu2018-01-161-0/+1
| | | | | | | test/Modules/odr_hash-Friend.cpp triggers an assertion in MicrosoftMangle.cpp This has been reported in PR35939 llvm-svn: 322593
* Move target MV resolver to COMDATErich Keane2018-01-167-15/+18
| | | | | | | | | | As reported here: https://bugs.llvm.org/show_bug.cgi?id=35921 The resolver functions should be in their own COMDAT regions. This patch sets that up. Differential Revision: https://reviews.llvm.org/D42110 llvm-svn: 322592
* [PPC] Add a new register XER aliased to CARRYGuozhi Wei2018-01-161-2/+6
| | | | | | | | | | When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler. This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly. Differential Revision: https://reviews.llvm.org/D41967 llvm-svn: 322591
* Inline foot gun into only valid use.Rafael Espindola2018-01-162-2/+4
| | | | | | | | | | | | | | Symbol had both Visibility and getVisibility() and they had different meanings. That is just too easy to get wrong. getVisibility() would compute the visibility of a particular symbol (foo in bar.o), and Visibility stores the computed value we will put in the output. There is only one case when we want what getVisibility() provides, so inline it. llvm-svn: 322590
* [DOCS] Updated current status of OpenMP support, NFC.Alexey Bataev2018-01-161-6/+6
| | | | llvm-svn: 322589
* [hwasan] Build runtime library with -fPIC, not -fPIE.Evgeniy Stepanov2018-01-161-1/+1
| | | | | | | | | | | | Summary: -fPIE can not be used when building a shared library. Reviewers: alekseyshl, peter.smith Subscribers: kubamracek, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D42121 llvm-svn: 322588
* [OPENMP] Add support for `depend` clauses on `target teams distributeAlexey Bataev2018-01-162-1/+262
| | | | | | | | | parallel for simd` directives. Added codegen for `depend` clauses on `#pragma omp target teams distribute parallel for simd` directives. llvm-svn: 322587
* Fix another case we used the wrong visibility.Rafael Espindola2018-01-163-2/+8
| | | | | | In here too we want the computed output visibility. llvm-svn: 322586
* [OPENMP] Add support for `depend` on `target teams distribute parallelAlexey Bataev2018-01-162-1/+267
| | | | | | | | | for` directives. Added codegen for `depend` clauses on `#pragma omp target teams distribute parallel for` directives. llvm-svn: 322585
* [CodeGen] Skip some instructions that shouldn't affect shrink-wrappingFrancis Visoiu Mistrih2018-01-161-5/+5
| | | | | | | | | | | r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs. This also skips IMPLICIT_DEFs and other instructions that may def / read a register. Differential Revision: https://reviews.llvm.org/D42119 llvm-svn: 322584
* Add an extra test. NFC.Rafael Espindola2018-01-162-0/+16
| | | | | | | Without this all test would pass if the visibility checks were removed from SymbolTable::addShared and SymbolTable::addUndefined. llvm-svn: 322583
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-169-53/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
* [IslTools] dumpPw: Dump same structure pieces together.Michael Kruse2018-01-161-21/+44
| | | | | | | | | | | | | | | | | | | | | | Print same or similar structure elements together. Previously, the value could take more importance that the space structure if visited first in the space nest tree. Before: { Left[0] -> Right[i]: i >= 0; Left[1] -> AnotherRight[i]; Left[2] -> Right[-1] } After: { Left[0] -> Right[i]: i >= 0; Left[2] -> Right[-1]; Left[1] -> AnotherRight[i] } llvm-svn: 322581
* Fix another case we were using the wrong visibility.Rafael Espindola2018-01-163-1/+13
| | | | llvm-svn: 322580
* [SLP] Fix for PR32164: Improve vectorization of reverse order of extract ↵Alexey Bataev2018-01-162-30/+33
| | | | | | | | | | | | | | operations. Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33954 llvm-svn: 322579
* [OPENMP] Add support for `depend` clauses on `target parallel for simd`Alexey Bataev2018-01-162-1/+262
| | | | | | | | | directives. Added codegen for `depend` clauses on `#pragma omp target parallel for simd` directives. llvm-svn: 322578
* [OPENMP] Add support for `depend` clauses on `target parallel for`Alexey Bataev2018-01-162-1/+262
| | | | | | | | | directives. Added codegen for `depend` clause on `#pragma omp target parallel for` directives. llvm-svn: 322577
* Use the combined visibility when computing dso_local.Rafael Espindola2018-01-162-3/+5
| | | | | | | | | | | We track both the combined visibility that will be used for the output symbol and the original input visibility of the selected symbol. Almost everything should use the computed visibility. I will make the names less confusing an a followup patch. llvm-svn: 322576
* [OPENMP] Add support for `depend` clauses on `target teams distributeAlexey Bataev2018-01-162-1/+262
| | | | | | | | | simd` directives. Added codegen for `depend` clauses on `#pragma omp target teams distribute simd` directives. llvm-svn: 322575
* [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMXSimon Pilgrim2018-01-162-81/+52
| | | | llvm-svn: 322574
* Add va_start()/va_copy()/va_end to Builtins.defNico Weber2018-01-161-0/+4
| | | | | | | That way, clang suggests including stdarg.h when these are used in C files. https://reviews.llvm.org/D42085 llvm-svn: 322573
* Set dso_local in lld.Rafael Espindola2018-01-166-9/+15
| | | | | | We were already doing this in gold, but not in lld. llvm-svn: 322572
* [OPENMP] Add support for `depend` clause on `target teams distribute`.Alexey Bataev2018-01-162-1/+262
| | | | | | | Added codegen for `depend` clauses on `#pragma omp target teams distribute` directives. llvm-svn: 322571
* [OPENMP] Add support for `depend` clauses on `target parallel` directive.Alexey Bataev2018-01-162-1/+262
| | | | | | | Added codegen for `depend` clauses on `#pragma omp target parallel` directives. llvm-svn: 322570
* [OPENMP] Add support for `depend` clauses on `target teams`.Alexey Bataev2018-01-162-1/+267
| | | | | | | Added codegen for `depend` clause on `#pragma omp target teams` directives. llvm-svn: 322569
* [LiveDebugValues] update kill-after-spill test with target triplePetar Jovanovic2018-01-161-0/+1
| | | | | | Set target triple to "x86_64-unknown-linux-gnu". llvm-svn: 322568
* More constexpr algorithms from P0202. search/search_nMarshall Clow2018-01-167-26/+101
| | | | llvm-svn: 322566
* [SystemZ] Support vector registers with inline asmUlrich Weigand2018-01-162-3/+21
| | | | | | | Allow using vector register names and the "v" constraint in inline asm to ensure compatibility with GCC. llvm-svn: 322562
* [OPENMP] Add support for `depend` clauses on `target simd`.Alexey Bataev2018-01-162-1/+262
| | | | | | | Added codegen for `depend` clauses on `#pragma omp target simd` directives. llvm-svn: 322559
* Change an internal table of constants for the poisson distribution fromMarshall Clow2018-01-161-1/+1
| | | | | | | | | type 'result_type' to 'double'. The only thing that we ever do with these numbers is to promote them to 'double' and use them in a division. For small result_types, the values were getting truncated, skewing the results. Thanks to James Nagurne for the suggestion. llvm-svn: 322556
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-162-7/+417
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [X86][MMX] Improve MMX constant generationSimon Pilgrim2018-01-163-26/+24
| | | | | | Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
* [NFC] fix trivial typos in documentsHiroshi Inoue2018-01-163-4/+4
| | | | | | "the the" -> "the" llvm-svn: 322552
* [NFC] fix trivial typo in documentHiroshi Inoue2018-01-161-1/+1
| | | | | | "the the" -> "the" llvm-svn: 322551
* Squash -Wcovered-switch-default wairningSam McCall2018-01-161-2/+1
| | | | llvm-svn: 322549
* Ensure code complete with !LoadExternal sees all local decls.Sam McCall2018-01-167-40/+35
| | | | | | | | | | | | | | | | | | | | | Summary: noload_lookups() was too lazy: in addition to avoiding external decls, it avoided populating the lazy lookup structure for internal decls. This is the right behavior for the existing callsite in ASTDumper, but I think it's not a very useful default, so we populate it by default. While here: - remove an unused test file accidentally added in r322371. - remove lookups_begin()/lookups_end() in favor of lookups().begin(), which is more common and more efficient. Reviewers: ilya-biryukov Subscribers: cfe-commits, rsmith Differential Revision: https://reviews.llvm.org/D42077 llvm-svn: 322548
* [clangd] Avoid combinatorial explosion in CodeCompleteTests.Sam McCall2018-01-161-20/+20
| | | | | | | | | | | | | | | | | Summary: This test dominates our unit test runtime, and the change speeds it up by 10x. We lose coverage of some combinations of flags, but I'm not sure that's finding many bugs. 3300 -> 300ms on my machine (3800 -> 800ms for the whole of CompletionTest). Reviewers: ilya-biryukov Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D42063 llvm-svn: 322547
* Add missing CINDEX_LINKAGEIvan Donchevskii2018-01-161-4/+4
| | | | | | | | Follow up for [libclang] Add PrintingPolicy for pretty printing declarations Differential Revision: https://reviews.llvm.org/D39903 llvm-svn: 322546
* [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC ↵Gadi Haber2018-01-1614-0/+16124
| | | | | | | | | | | | | | | encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC> NFC. Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. Started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D40879 Change-Id: I231a35861611bfd3d23c74cc59507373f021a629 llvm-svn: 322544
* [DebugInfo] Unify dumping of address rangesJonas Devlieghere2018-01-1653-223/+237
| | | | | | | | | | | | | | | Summary: This patch unifies the printing of address ranges as [0x0, 0x1). rdar://34822059 Reviewers: aprantl, dblaikie Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D42056 llvm-svn: 322543
* [CodeGen] Remove special case of printing subRegIdx from MachineInstr::printFrancis Visoiu Mistrih2018-01-161-3/+0
| | | | | | | Support in MachineOperand has been added in r320209. No need to special case this anymore. llvm-svn: 322542
* [CodeGen][NFC] Correct case for printSubRegIdxFrancis Visoiu Mistrih2018-01-165-5/+5
| | | | llvm-svn: 322541
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