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* Fix expectations in MC wasm init-fini-array testReid Kleckner2017-10-031-2/+7
| | | | llvm-svn: 314823
* Implement David Blaikie's suggestion for comparison operatorsReid Kleckner2017-10-031-3/+8
| | | | llvm-svn: 314822
* CodeView: Provide a .def file with the register idsHans Wennborg2017-10-038-243/+408
| | | | | | | | | | | | | | The list of register ids was previously written out in a couple of dirrent places. This puts it in a .def file and also adds a few more registers (e.g. the x87 regs) which should lead to more readable dumps, but I didn't include the whole list since that seems unnecessary. X86_MC::initLLVMToSEHAndCVRegMapping is pretty ugly, but at least it's not relying on magic constants anymore. The TODO of using tablegen still stands. Differential revision: https://reviews.llvm.org/D38480 llvm-svn: 314821
* [Analyzer] More granular special casing in RetainCountCheckerGeorge Karpenkov2017-10-032-3/+13
| | | | | | | | | Only assume that IOBSDNameMatching and friends increment a reference counter if their return type is a CFMutableDictionaryRef. Differential Revision: https://reviews.llvm.org/D38487 llvm-svn: 314820
* [DebugInfo] Correctly coalesce DBG_VALUEs that mix direct and indirect valuesReid Kleckner2017-10-033-85/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should fix a regression introduced by r313786, which switched from MachineInstr::isIndirectDebugValue() to checking if operand 1 is an immediate. I didn't have a test case for it until now. A single UserValue, which approximates a user variable, may have many DBG_VALUE instructions that disagree about whether the variable is in memory or in a virtual register. This will become much more common once we have llvm.dbg.addr, but you can construct such a test case manually today with llvm.dbg.value. Before this change, we would get two UserValues: one for direct and one for indirect DBG_VALUE instructions describing the same variable. If we build separate interval maps for direct and indirect locations, we will end up accidentally coalescing identical DBG_VALUE intervals that need to remain separate because they are broken up by intervals of the opposite direct-ness. Reviewers: aprantl Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37932 llvm-svn: 314819
* [test] Fix llvm-dwarfdump/cmdline.testJonas Devlieghere2017-10-031-1/+1
| | | | | | Fixes test/tools/llvm-dwarfdump/cmdline.test llvm-svn: 314818
* [dwarfdump] Add -lookup optionJonas Devlieghere2017-10-038-14/+385
| | | | | | | | | Add the option to lookup an address in the debug information and print out the file, function, block and line table details. Differential revision: https://reviews.llvm.org/D38409 llvm-svn: 314817
* [clang-tidy] fix buildbot hicpp-signed-bitwiseJonas Toth2017-10-031-1/+9
| | | | | | To finally fix the buildbot I added one single warning testcase. llvm-svn: 314816
* [X86] Add non-SSE tests for PR15215 as wellSimon Pilgrim2017-10-031-4/+76
| | | | llvm-svn: 314815
* Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source ↵Geoff Berry2017-10-0390-970/+372
| | | | | | | | | | forwarding"" This reverts commit r314729. Another bug has been encountered in an out-of-tree target reported by Quentin. llvm-svn: 314814
* [X86][SSE] Add bool vector extraction test cases from PR15215Simon Pilgrim2017-10-031-0/+134
| | | | llvm-svn: 314813
* [clang-tidy] potentially fix buildbot Jonas Toth2017-10-031-1/+1
| | | | | | | | I tried to silence lit with `| count 0`, which did not work. Other testcases did not have `-- --` but only `--` in the RUN line. Maybe this fixes the problem. llvm-svn: 314812
* [clang-tidy] Remove target specification hicpp-signed-bitwiseJonas Toth2017-10-031-1/+1
| | | | | | | | | | | This patch removes the targetspecification of a testcase, that broke for ARM. The underlying problem was fixed which makes it unnecessary to specify the target architecture (problem was the signedness of `char`). Committing without review was accepted in https://reviews.llvm.org/D38399 by aaron.ballman. llvm-svn: 314811
* Use sched_getaffinity instead of std::thread::hardware_concurrency.Rafael Espindola2017-10-031-2/+2
| | | | | | | | | | | | | | The issue with std::thread::hardware_concurrency is that it forwards to libc and some implementations (like glibc) don't take thread affinity into consideration. With this change a llvm program that can execute in only 2 cores will use 2 threads, even if the machine has 32 cores. This makes benchmarking a lot easier, but should also help if someone doesn't want to use all cores for compilation for example. llvm-svn: 314810
* Use sched_getaffinity instead of std::thread::hardware_concurrency.Rafael Espindola2017-10-039-17/+36
| | | | | | | | | | | | | | The issue with std::thread::hardware_concurrency is that it forwards to libc and some implementations (like glibc) don't take thread affinity into consideration. With this change a llvm program that can execute in only 2 cores will use 2 threads, even if the machine has 32 cores. This makes benchmarking a lot easier, but should also help if someone doesn't want to use all cores for compilation for example. llvm-svn: 314809
* [clang-tidy] Fix bug 34747, streaming operators and hicpp-signed-bitwiseJonas Toth2017-10-032-1/+24
| | | | | | | | | | | | The bug happened with stream operations, that were not recognized in all cases. Even there were already existing test for streaming classes, they did not catch this bug. Adding the isolated example to the existing tests did not trigger the bug. Therefore i created a new isolated file that did expose the bug indeed. Differential: https://reviews.llvm.org/D38399 reviewed by aaron.ballman llvm-svn: 314808
* Revert the change that accidentally went in r314806.Dehao Chen2017-10-031-4/+0
| | | | llvm-svn: 314807
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-10-037-136/+373
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: hans, mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 llvm-svn: 314806
* [Dominators] Don't use default parameter in lambdaJakub Kuderski2017-10-031-3/+3
| | | | | | ... to make GCC buildbots happy. llvm-svn: 314805
* [ARM] Use table-gen'd assembly operand diags in ARM asm parserOliver Stannard2017-10-035-98/+25
| | | | | | | | | | | | This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
* [AsmParser] Add DiagnosticString to AsmOperands in tablegenOliver Stannard2017-10-032-2/+51
| | | | | | | | | | | | | | This adds a DiagnosticString member to the AsmOperand tablegen class, so that the diagnostic text to be used when an assembly operand is incorrect can be stored in the tablegen description of the operand, rather than in a separate switch statement in the AsmParser. If DiagnosticString is used for any operands, tablegen will emit a getMatchKindDiag function, to map from diagnostic enums to strings. Differential revision: https://reviews.llvm.org/D31606 llvm-svn: 314803
* [OpenCL] Fix checking of vector type castingYaxun Liu2017-10-032-4/+12
| | | | | | | | | | | | | | | | | | Currently clang allows the following code int a; int b = (const int) a; However it does not the following code int4 a; int4 b = (const int4) a; This is because Clang compares the qualified types instead of unqualified types for vector type casting, which causes the inconsistency. This patch fixes that. Differential Revision: https://reviews.llvm.org/D38463 llvm-svn: 314802
* [Dominators] Add DFS number verificationJakub Kuderski2017-10-032-12/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch teaches the DominatorTree verifier to check DFS In/Out numbers which are used to answer dominance queries. DFS number verification is done in O(nlogn), so it shouldn't add much overhead on top of the O(n^3) sibling property verification. This check should detect errors like the one spotted in PR34466 and related bug reports. The patch also cleans up the DFS calculation a bit, as all constructed trees should have a single root now. I see 2 new test failures when running check-all after this change: ``` Failing Tests (2): Polly :: Isl/CodeGen/OpenMP/reference-argument-from-non-affine-region.ll Polly :: Isl/CodeGen/OpenMP/two-parallel-loops-reference-outer-indvar.ll ``` which seem to happen just after `Create LLVM-IR from SCoPs` -- I XFAILed them in r314800. Reviewers: dberlin, grosser, davide, zhendongsu, bollu Reviewed By: dberlin Subscribers: nandini12396, bollu, Meinersbur, brzycki, llvm-commits Differential Revision: https://reviews.llvm.org/D38331 llvm-svn: 314801
* XFAIL two test that fail VerifyDFSNumbers DominatorTree checkJakub Kuderski2017-10-032-0/+6
| | | | | | | | | This test XFAILs two test that start to fail when verifying DT's DFS numbers, as per Tobias' suggestion. Related VerifyDFSNumbers patch: D38331. llvm-svn: 314800
* [ARM, Asm] Use correct source location for register tokensOliver Stannard2017-10-032-3/+15
| | | | | | | | | | | | tryParseRegister advances the lexer, so we need to take copies of the start and end locations of the register operand before calling it. Previously, the caret in the diagnostic pointer to the comma after the r0 operand in the test, rather than the start of the operand. Differential revision: https://reviews.llvm.org/D31537 llvm-svn: 314799
* [mips] Enable spilling and reloading of the dsp register set.Simon Dardis2017-10-034-0/+69
| | | | | | | | | | | The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 llvm-svn: 314798
* [MIPS] Generate thunks for microMIPS codeSimon Atanasyan2017-10-035-7/+133
| | | | | | | | If symbol has the STO_MIPS_MICROMIPS flag and requires a thunk to perform call PIC from non-PIC functions, we need to generate a thunk with microMIPS code. llvm-svn: 314797
* [CGP] Make optimizeMemoryInst capable of handling multiple AddrModesJohn Brawn2017-10-031-20/+154
| | | | | | | | | | | | | Currently optimizeMemoryInst requires that all of the AddrModes it sees are identical. This patch makes it capable of tracking multiple AddrModes, so long as they differ in at most one field. This patch does nothing by itself, but later patches will make use of it to insert or reuse phi or select instructions for the differing fields. Differential Revision: https://reviews.llvm.org/D38278 llvm-svn: 314795
* [CGP] In optimizeMemoryInst handle select similarly to phiJohn Brawn2017-10-032-7/+33
| | | | | | | | | | This lets us optimize away selects that perform the same address computation in two different ways and is also the first step towards being able to handle selects between two different, but compatible, address computations. Differential Revision: https://reviews.llvm.org/D38242 llvm-svn: 314794
* [ARM, Asm] Fix ubsan failure caused by out-of-range enum valueOliver Stannard2017-10-031-2/+2
| | | | | | | | In this code, we use ~0U as a sentinel value for any operand class that doesn't have a user-friendly error message, but this value isn't in range of the MatchClassKind enum, so we need to ensure it does not get passed to isSubclass. llvm-svn: 314793
* [X86][SSE] Add support for decoding PACKSS/PACKUS shuffles masks with UNDEFSimon Pilgrim2017-10-032-10/+16
| | | | llvm-svn: 314792
* [ARM, Asm] Remove dead code causing MSan failure.Oliver Stannard2017-10-031-7/+0
| | | | | | | r314779 caused ErrorInfo to be red uninitialised, but also made this code dead, so it can just be removed. llvm-svn: 314791
* [ELF] Avoid promoting an undefined weak entry symbol to global.Igor Kudrin2017-10-034-10/+33
| | | | | | | Without this patch, lld emits "error: undefined symbol: _start" if it encountered only weak references to that symbol. llvm-svn: 314790
* [ELF] Keep symbols specified by '-u' over LTO.Igor Kudrin2017-10-032-3/+28
| | | | | | Differential Revision: https://reviews.llvm.org/D38348 llvm-svn: 314789
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-0317-491/+425
| | | | | | | | | | If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles. Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773 Differential Revision: https://reviews.llvm.org/D38472 llvm-svn: 314788
* [InlineCost, NFC] Extract code dealing with inbounds GEPs from ↵Evgeny Astigeevich2017-10-031-29/+24
| | | | | | | | | | | | | visitGetElementPtr into a function The code responsible for analysis of inbounds GEPs is extracted into a separate function: CallAnalyzer::canFoldInboundsGEP. With the patch SROA enabling/disabling code is localized at one place instead of spreading across the code of CallAnalyzer::visitGetElementPtr. Differential Revision: https://reviews.llvm.org/D38233 llvm-svn: 314787
* Revert "[XRay][compiler-rt] Use a hand-written circular buffer in BufferQueue"Dean Michael Berris2017-10-033-88/+32
| | | | | | This reverts r314766 (rL314766). Unit tests fail in multiple bots. llvm-svn: 314786
* [clang-tidy] Fixed a small code example in docs. NFC.Gabor Horvath2017-10-031-1/+1
| | | | llvm-svn: 314785
* [CodeGen] Fix propagation of TBAA info for atomic accessesIvan A. Kosarev2017-10-031-4/+4
| | | | | | | | | | | | | This patch fixes clang to propagate complete TBAA information for atomic accesses and not just the final access types. Prepared against D38456 and requires it to be committed first. This is part of D37826 reworked to be a separate patch to simplify review. Differential Revision: https://reviews.llvm.org/D38460 llvm-svn: 314784
* [WebAssembly] MC: Support for init_array and fini_arraySam Clegg2017-10-032-3/+101
| | | | | | Differential Revision: https://reviews.llvm.org/D37757 llvm-svn: 314783
* [llvm-cov] Hide files with no coverage from the index when filtering by nameSean Eveson2017-10-038-12/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D38457 llvm-svn: 314782
* [DebugInfo] Handle endianness when moving debug info for split integer ↵Bjorn Pettersson2017-10-032-2/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values (reapplied) Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Original patch was reverted due to using -stop-after=isel in the test case (but that is only working when AMDGPU target is included in the llc build). The test case has now been updated to use -stop-before=expand-isel-pseudos instead. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314781
* [CodeGen] Introduce generic TBAA access descriptorsIvan A. Kosarev2017-10-037-83/+82
| | | | | | | | | | | | | With this patch we implement a concept of TBAA access descriptors that are capable of representing both scalar and struct-path accesses in a generic way. This is part of D37826 reworked to be a separate patch to simplify review. Differential Revision: https://reviews.llvm.org/D38456 llvm-svn: 314780
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-0343-2134/+2465
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* Remove unused variable. NFCI.Simon Pilgrim2017-10-031-1/+0
| | | | llvm-svn: 314778
* [X86][SSE] Add support for shuffle combining from PACKSS/PACKUSSimon Pilgrim2017-10-032-16/+8
| | | | | | Mentioned in D38472 llvm-svn: 314777
* [X86][SSE] Add support for PACKSS/PACKUS constant foldingSimon Pilgrim2017-10-034-68/+133
| | | | | | Pulled out of D38472 llvm-svn: 314776
* [MiSched] - Simplify ProcResEntry accessJaved Absar2017-10-031-6/+8
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38447 llvm-svn: 314775
* [Assembler] Report multiple near misses for invalid instructionsOliver Stannard2017-10-033-66/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current table-generated assembly instruction matcher returns a 64-bit error code when matching fails. Since multiple instruction encodings with the same mnemonic can fail for different reasons, it uses some heuristics to decide which message is important. This heuristic does not work well for targets that have many encodings with the same mnemonic but different operands, or which have different versions of instructions controlled by subtarget features, as it is hard to know which encoding the user was intending to use. Instead of trying to improve the heuristic in the table-generated matcher, this patch changes it to report a list of near-miss encodings. This list contains an entry for each encoding with the correct mnemonic, but with exactly one thing preventing it from being valid. This thing could be a single invalid operand, a missing target feature or a failed target-specific validation function. The target-specific assembly parser can then report an error message giving multiple options for instruction variants that the user may have been trying to use. For example, I am working on a patch to use this for ARM, which can give this error for an invalid instruction for ARMv6-M: <stdin>:8:3: error: invalid instruction, multiple near-miss encodings found adds r0, r1, #0x8 ^ <stdin>:8:3: note: for one encoding: instruction requires: thumb2 adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected an integer in range [0, 7] adds r0, r1, #0x8 ^ <stdin>:8:16: note: for one encoding: expected a register in range [r0, r7] adds r0, r1, #0x8 ^ This also allows the target-specific assembly parser to apply its own heuristics to suppress some errors. For example, the error "instruction requires: arm-mode" is never going to be useful when targeting an M-profile architecture (which does not have ARM mode). This patch just adds the target-independent mechanism for doing this, all targets still use the old mechanism. I've added a bit in the AsmParser tablegen class to allow targets to switch to this new mechanism. To use this, the target-specific assembly parser will have to be modified for the change in signature of MatchInstructionImpl, and to report errors based on the list of near-misses. Differential revision: https://reviews.llvm.org/D27620 llvm-svn: 314774
* ISel type legalization: add debug messages. NFCI.Sjoerd Meijer2017-10-032-168/+197
| | | | | | | | | | This adds some more debug messages to the type legalizer and functions like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make the debug messages a little bit more informative and useful. Differential Revision: https://reviews.llvm.org/D38450 llvm-svn: 314773
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