| Commit message (Collapse) | Author | Age | Files | Lines |
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and output expressions much like that in GNU-style inline assembly. Output
expressions are first. Do this for MS-style inline asms.
llvm-svn: 163342
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virtual step.
llvm-svn: 163341
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llvm-svn: 163340
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No functional change.
llvm-svn: 163339
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// rdar://12233989
llvm-svn: 163338
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crash in a corner case. Patch by Olivier Goffart!
llvm-svn: 163337
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The RegisterCoalescer understands overlapping live ranges where one
register is defined as a copy of the other. With this change, register
allocators using LiveRegMatrix can do the same, at least for copies
between physical and virtual registers.
When a physreg is defined by a copy from a virtreg, allow those live
ranges to overlap:
%CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11
%vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill>
We can assign %vreg11 to %ECX, overlapping the live range of %CL.
llvm-svn: 163336
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We will soon allow virtual register live ranges to overlap regunit live
ranges when the physreg is defined as a copy of the virtreg:
%EAX = COPY %vreg5
FOO %vreg5
BAR %EAX<kill>
There is no real interference since %vreg5 and %EAX have the same value
where they overlap.
This patch prevents addKillFlags from adding virtreg kill flags to FOO
where the assigned physreg is overlapping the virtual register live
range.
llvm-svn: 163335
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Kill flags are difficult to maintain, and liveness queries are better
handled by live intervals.
Kill flags are reinserted after register allocation by addKillFlags().
llvm-svn: 163334
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This patch uses a new ABIInfo implementation specific to the le32
target, rather than falling back to DefaultABIInfo. Its behavior is
basically the same, but it also allows the regparm argument attribute.
It also includes basic tests for argument codegen and attributes.
llvm-svn: 163333
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llvm-svn: 163332
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ifdef'ed out. This change is required to support enhancements in the LLDB data formatters
llvm-svn: 163331
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Patch thanks to Joe Ranieri!
llvm-svn: 163330
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Don't warn if annotated decl is used inside another
unused. // rdar://12233989
llvm-svn: 163329
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These tests were failing for me because the .* was greedily matching up
to the /libexec/ld-elf.so.1" later on the same line.
llvm-svn: 163328
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llvm-svn: 163327
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llvm-svn: 163326
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llvm-svn: 163325
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llvm-svn: 163324
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Patch by Chris Lidbury.
llvm-svn: 163323
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time (by not memorizing full stacks in traces)
llvm-svn: 163322
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instructions.
Patch by Chris Lidbury.
llvm-svn: 163321
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llvm-svn: 163320
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Enhances basic alias analysis to recognize phis whose first incoming values are
NoAlias and whose other incoming values are just the phi node itself through
some amount of recursion.
Example: With this change basicaa reports that ptr_phi and ptr_phi2 do not alias
each other.
bb:
ptr = ptr2 + 1
loop:
ptr_phi = phi [bb, ptr], [loop, ptr_plus_one]
ptr2_phi = phi [bb, ptr2], [loop, ptr2_plus_one]
...
ptr_plus_one = gep ptr_phi, 1
ptr2_plus_one = gep ptr2_phi, 1
This enables the elimination of one load in code like the following:
extern int foo;
int test_noalias(int *ptr, int num, int* coeff) {
int *ptr2 = ptr;
int result = (*ptr++) * (*coeff--);
while (num--) {
*ptr2++ = *ptr;
result += (*coeff--) * (*ptr++);
}
*ptr = foo;
return result;
}
Part 2/2 of fix for PR13564.
llvm-svn: 163319
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Patch by Chris Lidbury.
llvm-svn: 163318
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If we can show that the base pointers of two GEPs don't alias each other using
precise analysis and the indices and base offset are equal then the two GEPs
also don't alias each other.
This is primarily needed for the follow up patch that analyses NoAlias'ing PHI
nodes.
Part 1/2 of fix for PR13564.
llvm-svn: 163317
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llvm-svn: 163316
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This Operand type takes a default argument, and is initialized to
this value if it does not appear in a patter.
llvm-svn: 163315
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variadic macros, signed vs. unsigned comparison.
llvm-svn: 163314
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llvm-svn: 163313
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Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible.
llvm-svn: 163312
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llvm-svn: 163311
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llvm-svn: 163309
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llvm-svn: 163308
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llvm-svn: 163307
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llvm-svn: 163306
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The lookup tables did not get built in a deterministic order.
This makes them get built in the order that the corresponding phi nodes
were found.
llvm-svn: 163305
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If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base.
llvm-svn: 163304
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llvm-svn: 163303
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This adds a transformation to SimplifyCFG that attemps to turn switch
instructions into loads from lookup tables. It works on switches that
are only used to initialize one or more phi nodes in a common successor
basic block, for example:
int f(int x) {
switch (x) {
case 0: return 5;
case 1: return 4;
case 2: return -2;
case 5: return 7;
case 6: return 9;
default: return 42;
}
This speeds up the code by removing the hard-to-predict jump, and
reduces code size by removing the code for the jump targets.
llvm-svn: 163302
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This should fix http://code.google.com/p/address-sanitizer/issues/detail?id=105
llvm-svn: 163301
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llvm-svn: 163300
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allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
llvm-svn: 163299
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to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer.
llvm-svn: 163298
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testing purposes)
llvm-svn: 163297
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llvm-svn: 163296
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llvm-svn: 163295
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llvm-svn: 163294
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lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder.
llvm-svn: 163293
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of a 256-bit vector to VMOVAPSmr/VMOVUPSmr.
llvm-svn: 163292
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