| Commit message (Collapse) | Author | Age | Files | Lines |
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r210369 didn't quite catch all of them.
llvm-svn: 210593
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We preivously had two copies of ::BytesAvailable with only trivial
differences between them, and fixes have been applied to only one of
them.
Instead of duplicating the whole function, hide the FD_SET differences
behind a macro. This leaves only one small __APPLE__-specific #if
block, and fixes ^C on non-__APPLE__ platforms.
llvm-svn: 210592
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This reduces the difference between std::error_code and llvm::error_code.
llvm-svn: 210591
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llvm-svn: 210590
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of using the cached TargetMachine.
llvm-svn: 210589
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I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.
v2:
- Fix build
v3:
- Added crash fix when spilling SPGRs
v4:
- Use V_MOV_B32 as a dummy instruction instead of S_NOP
Patch by: Darren Powell
https://bugs.freedesktop.org/show_bug.cgi?id=75276
llvm-svn: 210588
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We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.
This fixes a crash in the game Antichamber.
https://bugs.freedesktop.org/show_bug.cgi?id=75276
llvm-svn: 210587
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llvm-svn: 210586
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llvm-svn: 210585
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The changes in r204978 broke win32-macho targets. There were checks added for
MSVC and Itanium environments as special cases, and win32-macho needs to be
treated the same way.
llvm-svn: 210584
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No functionality change.
llvm-svn: 210583
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Patch by Ehsan Akhgari! (Test tweak by me.)
Differential Revision: http://reviews.llvm.org/D4065
llvm-svn: 210582
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This will be needed for the switch to std::error_code.
llvm-svn: 210581
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llvm-svn: 210580
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version of TargetLowering/Machine from there on the way to avoiding
TargetMachine in TargetLowering.
llvm-svn: 210579
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llvm-svn: 210578
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http://llvm.org/bugs/show_bug.cgi?id=18681
Patch by Ryuta Suzuki <oroppas gmail com>
llvm-svn: 210577
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Reported-by: Jules Gagnon-Marchand <jules_gagnonm@hotmail.com>
llvm-svn: 210576
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llvm-svn: 210575
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This reverts commit r206683.
The code was confusing SEH register numbers with DWARF register numbers.
The test case it was committed with was obviously incorrect. The
disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg
%rbp', and other exciting things.
Noticed by Vadim Chugunov.
llvm-svn: 210574
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Right now it just checks that qSupported returns at least
one recognized gdb stub feature.
llvm-svn: 210573
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!if([Something], []) would error with "No type for list".
llvm-svn: 210572
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llvm-svn: 210571
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llvm-svn: 210570
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llvm-svn: 210569
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llvm-svn: 210568
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llvm-svn: 210567
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llvm-svn: 210566
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doing Objective-C subscript access. // rdar://16842487
PR19682.
llvm-svn: 210565
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llvm-svn: 210564
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llvm-svn: 210563
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return void in C++11
llvm-svn: 210562
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of refacoring in algorithm as well. Give them better names while we're at it. All of these are internal rotines; no visible functionality change.
llvm-svn: 210561
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bits out on c++03, since it doesn't support u"" and U "" style strings.
llvm-svn: 210560
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llvm-svn: 210559
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llvm-svn: 210558
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llvm-svn: 210557
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Add more instruction-specific statistics about failing intrinsic calls during
FastISel.
llvm-svn: 210556
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of the DataLayout.
llvm-svn: 210555
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than a TargetMachine.
llvm-svn: 210554
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llvm-svn: 210553
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llvm-svn: 210552
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llvm-svn: 210551
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We would previously end up with an error when instantiating the
following template:
template <typename> struct __declspec(dllimport) S {
void foo() = delete;
};
S<int> s;
error: attribute 'dllimport' cannot be applied to a deleted function
llvm-svn: 210550
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llvm-svn: 210549
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AArch64FrameLowering.
llvm-svn: 210548
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'super' dispatches a class method in category for OBJC_METACLASS.
This is when class is a weak_import class.
// rdar://16529125
llvm-svn: 210547
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Summary:
Implement materialize of floating point literals in Mips Fast-Isel
Reopened version of D3659
Test Plan: simplestorefp1.ll
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4071
llvm-svn: 210546
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This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for
the VEX.256 encoded versions of horizontal add/sub.
For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.
Added a new test case into haddsub-2.ll.
llvm-svn: 210545
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il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.
llvm-svn: 210544
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