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* AMDGPU: Correct properties for adjcallstack* pseudosMatt Arsenault2019-07-014-13/+17
| | | | | | | These should be SALU writes, and these are lowered to instructions that def SCC. llvm-svn: 364859
* Fix broken C++ mode commentMatt Arsenault2019-07-011-1/+1
| | | | llvm-svn: 364858
* [InstCombine][NFCI] Update test cases in onehot_merge.llHuihui Zhang2019-07-011-8/+46
| | | | | | | | | | | | | | | | Use both one bit and signbit shifting to check for one bit merge. Reviewers: lebedev.ri, spatel, efriedma, craig.topper Reviewed By: lebedev.ri Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63903 llvm-svn: 364857
* [InstCombine] reduce more checks for power-of-2-or-zero using ctpopSanjay Patel2019-07-012-40/+30
| | | | | | | | | Extends the transform from: rL364341 ...to include another (more common?) pattern that tests whether a value is a power-of-2 (including or excluding zero). llvm-svn: 364856
* Fix breakage introduced by D60974JF Bastien2019-07-011-0/+1
| | | | | | D60974 added tests which incorrectly assume that llvm-readelf is available. This is a bad assumption, it should instead declare the dependency explicitly in the tests. llvm-svn: 364855
* [Reproducer] Assert on unexpected packetJonas Devlieghere2019-07-011-0/+1
| | | | | | | | I'm not able to reproduce the reproducer flakiness we're seeing on GreenDragon. I want to add this assert to find out if the GDB remote packets are somehow getting out of sync when this happens. llvm-svn: 364852
* [X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where ↵Craig Topper2019-07-013-9/+7
| | | | | | | | | | | | only 32-bits are loaded. v2i64 vzload defines a 64-bit memory access. It doesn't look like we have any coverage for this either way. Also remove some vzload usages where the instruction loads only 16-bits. llvm-svn: 364851
* [mips] Add missing schedinfo for MIPSeh_return[32|64] instructionsSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364850
* [mips] Add virtualization ASE to P5600 scheduling definitionsSimon Atanasyan2019-07-011-0/+5
| | | | llvm-svn: 364849
* [mips] Add missing schedinfo for LONG_BRANCH_* instructionsSimon Atanasyan2019-07-012-11/+27
| | | | llvm-svn: 364848
* [X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX.Craig Topper2019-07-012-12/+0
| | | | | | | These patterns all matched a v2i64 vzload which only loads 64-bits to instructions that load a full 128-bits. llvm-svn: 364847
* Revert [SLP] Look-ahead operand reordering heuristic.Jordan Rupprecht2019-07-012-323/+93
| | | | | | | | This reverts r364478 (git commit 574cb0eb3a7ac95e62d223a60bef891171dfe321) The patch is causing compilation timeouts. llvm-svn: 364846
* [Core] Generalize ValueObject::IsRuntimeSupportValueAlex Langford2019-07-018-47/+36
| | | | | | | | | | | | | | | Summary: Instead of falling back to ObjCLanguageRuntime, we should be falling back to every loaded language runtime. This makes ValueObject more language agnostic. Reviewers: labath, compnerd, JDevlieghere, davide Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D63240 llvm-svn: 364845
* [NFC][InstCombine] More commutative tests for "shift direction in bittest" ↵Roman Lebedev2019-07-011-16/+61
| | | | | | | | | (PR42466) 'and' is commutative, if we don't want to touch shift-of-const, we still need to check the other hand of 'and'. llvm-svn: 364844
* Testing commit access through minor formatting changeNilanjana Basu2019-07-011-2/+3
| | | | llvm-svn: 364843
* Ensure bitset's string constructor doesn't poison the overload set.Eric Fiselier2019-07-013-2/+19
| | | | llvm-svn: 364842
* GlobalISel: Try to widen merges with other mergesMatt Arsenault2019-07-012-20/+355
| | | | | | | | If the requested source type an be used as a merge source type, create a merge of merges. This avoids creating large, illegal extensions and bit-ops directly to the result type. llvm-svn: 364841
* Implement P0646R1: Erase-Like Algorithms Should Return size_type. Reviewed ↵Marshall Clow2019-07-018-75/+84
| | | | | | as https://reviews.llvm.org/D58332, and then updated because I rewrote a couple of those routines to eliminate some UB. Thanks to Zoe for tghe patch. llvm-svn: 364840
* AMDGPU: Revert accidental change to testMatt Arsenault2019-07-011-1/+1
| | | | llvm-svn: 364839
* [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patternsCraig Topper2019-07-015-156/+147
| | | | | | | | | | | | | | | These instructions only read 64-bits of memory so we shouldn't allow a full vector width load to be pattern matched in case it is marked volatile. Instead allow vzload or scalar_to_vector+load. Also add a DAG combine to turn full vector loads into vzload when used by one of these instructions if the load isn't volatile. This fixes another case for PR42079 llvm-svn: 364838
* Fixed two issues in clang-tidy -help.Alexander Kornienko2019-07-013-108/+108
| | | | | | HeaderFilter -> HeaderFilterRegex llvm-svn: 364837
* AMDGPU/GlobalISel: Handle more input argument intrinsicsMatt Arsenault2019-07-019-52/+155
| | | | llvm-svn: 364836
* AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsicsMatt Arsenault2019-07-015-43/+173
| | | | llvm-svn: 364835
* AMDGPU/GlobalISel: Legalize workgroup ID intrinsicsMatt Arsenault2019-07-014-0/+257
| | | | llvm-svn: 364834
* AMDGPU/GlobalISel: Legalize workitem ID intrinsicsMatt Arsenault2019-07-016-2/+222
| | | | | | | | | Tests don't cover the masked input path since non-kernel arguments aren't lowered yet. Test is copied directly from the existing test, with 2 additions. llvm-svn: 364833
* AMDGPU/GlobalISel: Custom lower control flow intrinsicsMatt Arsenault2019-07-014-11/+256
| | | | | | | | Replace the brcond for the 2 cases that act as branches. For now follow how the current system works, although I think we can eventually get rid of the pseudos. llvm-svn: 364832
* AMDGPU/GlobalISel: Handle 16-bit SALU min/maxMatt Arsenault2019-07-015-65/+391
| | | | | | | | | This needs to be extended to s32, and expanded into cmp+select. This is relying on the fact that widenScalar happens to leave the instruction in place, but this isn't a guaranteed property of LegalizerHelper. llvm-svn: 364831
* AMDGPU/GlobalISel: Lower SALU min/max to cmp+selectMatt Arsenault2019-07-015-86/+297
| | | | | | | Use a change observer to apply a register bank to the newly created intermediate result register. llvm-svn: 364830
* [X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)Robert Lougher2019-07-013-0/+425
| | | | | | | | | | | | | | The function findPotentialBlockers may consider debug info instructions as potential blockers and may stop searching for a store-load pair prematurely. This patch corrects this and tests the cases where the store is separated from the load by more than InspectionLimit debug instructions. Patch by Chris Dawson. Differential Revision: https://reviews.llvm.org/D62408 llvm-svn: 364829
* AMDGPU/GlobalISel: Add tests for add legalizationMatt Arsenault2019-07-011-0/+87
| | | | llvm-svn: 364828
* AMDGPU/GlobalISel: Legalize s16 add/sub/mulMatt Arsenault2019-07-015-60/+604
| | | | | | | If this is scalar, promote to s32. Use a new observer class to assign the register bank of newly created registers. llvm-svn: 364827
* [lldb] [lldbsuite] Use a unique class name for TestBacktraceAllStella Stamenova2019-07-011-1/+1
| | | | | | It looks like when this test was added, it was based on TestBreakAfterJoin and it ended up with the same class name. This is an issue because the logs associated with the tests use the class name as the identifier for the file and if two tests have the same name their logs overwrite each other. On non-windows, this just means we lose one of the logs, but on Windows this means that one of the tests will fail occasionally because the file are locked by the other test. llvm-svn: 364826
* AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECTMatt Arsenault2019-07-013-1077/+2252
| | | | | | | | | The condition register bank must be scc or vcc so that a copy will be inserted, which will be lowered to a compare. Currently greedy unnecessarily forces using a VCC select. llvm-svn: 364825
* [NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466)Roman Lebedev2019-07-011-0/+234
| | | | | | | https://rise4fun.com/Alive/8O1 https://bugs.llvm.org/show_bug.cgi?id=42466 llvm-svn: 364824
* [TSan] Fix initialized and declared ‘extern’ warningJulian Lettner2019-07-011-2/+5
| | | | | | | | | | | | Avoid the following warning which fails a bot (via -Werror). ``` /tmp/gotsan.JfrpVPu7pG/gotsan.cc:10456:25: error: ‘_tsan_pointer_chk_guard’ initialized and declared ‘extern’ [-Werror] extern "C" __tsan::uptr _tsan_pointer_chk_guard = 0; ^~~~~~~~~~~~~~~~~~~~~~~ ``` llvm-svn: 364823
* GlobalISel: Verify G_MERGE_VALUES operand sizesMatt Arsenault2019-07-012-0/+38
| | | | llvm-svn: 364822
* [GlobalISel]: Allow backends to custom legalize IntrinsicsAditya Nandakumar2019-07-013-0/+15
| | | | | | | | | https://reviews.llvm.org/D31359 Add a hook "legalizeInstrinsic" to allow backends to override this and custom lower/legalize intrinsics. llvm-svn: 364821
* [OPENMP]Fix handling of lambda captures in target regions.Alexey Bataev2019-07-014-58/+55
| | | | | | | | Previously, lambda captures were processed in the function called during capturing the variables. It leads to the recursive functions calls and may result in the compiler crash. llvm-svn: 364820
* AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghaltMatt Arsenault2019-07-013-3/+93
| | | | llvm-svn: 364819
* [TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.2Julian Lettner2019-07-012-8/+4
| | | | | | | | | | | | Switch `LongJmp` over to lookup JmpBuf via plain old (unmangled) SP. This makes the computation of mangled SPs in the TSan assembly files unnecessary, which will be cleaned up in follow-up revisions. Reviewed By: dvyukov Differential Revision: https://reviews.llvm.org/D63942 llvm-svn: 364818
* AMDGPU/GlobalISel: Legalize s16 fcmpMatt Arsenault2019-07-012-70/+261
| | | | llvm-svn: 364817
* GlobalISel: Implement lower for min/maxMatt Arsenault2019-07-013-0/+115
| | | | llvm-svn: 364816
* AMDGPU/GFX10: implement ds_ordered_count changesNicolai Haehnle2019-07-013-1/+46
| | | | | | | | | | | | | | | | | | | Summary: ds_ordered_count can now simultaneously operate on up to 4 dwords in a single instruction, which are taken from (and returned to) lanes 0..3 of a single VGPR. Change-Id: I19b6e7b0732b617c10a779a7f9c0303eec7dd276 Reviewers: mareko, arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63716 llvm-svn: 364815
* AMDGPU: Support GDS atomicsNicolai Haehnle2019-07-019-54/+225
| | | | | | | | | | | | | | | | | Summary: Original patch by Marek Olšák Change-Id: Ia97d5d685a63a377d86e82942436d1fe6e429bab Reviewers: mareko, arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63452 llvm-svn: 364814
* [ELF][RISCV] Support GD/LD/IE/LE TLS modelsFangrui Song2019-07-017-3/+377
| | | | | | | | | | | | RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
* [ELF][RISCV] Support PLT, GOT, copy and relative relocationsFangrui Song2019-07-018-4/+365
| | | | | | | | | | | | | | | | | | | | * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
* AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swapMatt Arsenault2019-07-014-2/+174
| | | | llvm-svn: 364811
* AArch64/GlobalISel: Fix trying to select invalid MIRMatt Arsenault2019-07-011-18/+15
| | | | | | Physical registers are not allowed to be a phi operand. llvm-svn: 364810
* Summary: [Clangd] Added hidden command line option -tweaks to specify which ↵Shaurya Gupta2019-07-014-3/+20
| | | | | | | | | | | | | | | | tweaks to enable - Only for development purposes - Disabled tweaks in fixits-duplications test Reviewers: sammccall, kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63989 llvm-svn: 364809
* AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelaneMatt Arsenault2019-07-012-5/+156
| | | | llvm-svn: 364808
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