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* [APInt] Fix typo in comment. NFCCraig Topper2017-05-111-1/+1
| | | | llvm-svn: 302815
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-1111-169/+78
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault2017-05-116-8/+72
| | | | | | | This allows folding source modifiers in more f16 cases. Makes it easier to select per-component packed neg modifiers. llvm-svn: 302813
* [AMDGPU] Fix incorrect register pressure calculationStanislav Mekhanoshin2017-05-111-2/+3
| | | | | | | | | Earlier fix D32572 introduced a bug where live-ins were calculated for basic block instead of scheduling region. This change fixes it. Differential Revision: https://reviews.llvm.org/D33086 llvm-svn: 302812
* [SLP] Emit optimization remarksAdam Nemet2017-05-115-11/+143
| | | | | | | | | | | | | | | | | | The approach I followed was to emit the remark after getTreeCost concludes that SLP is profitable. I initially tried emitting them after the vectorizeRootInstruction calls in vectorizeChainsInBlock but I vaguely remember missing a few cases for example in HorizontalReduction::tryToReduce. ORE is placed in BoUpSLP so that it's available from everywhere (notably HorizontalReduction::tryToReduce). We use the first instruction in the root bundle as the locator for the remark. In order to get a sense how far the tree is spanning I've include the size of the tree in the remark. This is not perfect of course but it gives you at least a rough idea about the tree. Then you can follow up with -view-slp-tree to really see the actual tree. llvm-svn: 302811
* [PowerPC] Eliminate integer compare instructions - vol. 1Nemanja Ivanovic2017-05-1118-11/+1942
| | | | | | | | | | | | | This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
* Add a test that local submodule visibility has no effect on debug infoAdrian Prantl2017-05-111-0/+5
| | | | | | rdar://problem/27876262 llvm-svn: 302809
* [DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.Simon Pilgrim2017-05-111-18/+4
| | | | llvm-svn: 302808
* [asan] Test 'strndup_oob_test.cc' added in r302781 fails on the ↵Pierre Gousseau2017-05-111-1/+2
| | | | | | | | clang-cmake-thumbv7-a15-full-sh bot. Marking as unsupported on armv7l-unknown-linux-gnueabihf, same as strdup_oob_test.cc llvm-svn: 302807
* Fix -DLLVM_ENABLE_THREADS=OFF build after r302748Hans Wennborg2017-05-111-0/+2
| | | | llvm-svn: 302806
* [Simplify] Remove identical scalar writes.Michael Kruse2017-05-117-1/+428
| | | | | | | | | | | | | | | | | | | | | | After DeLICM, it is possible to have two writes of the same value to the same location in the same statement when it determined that those writes do not conflict (write the same value). Teach -polly-simplify to remove one of the writes. It interferes with the pattern matching of matrix-multiplication kernels and also seem to not be optimized away by LLVM. The algorthm is simple, has O(n^2) behaviour (n = max number of MemoryAccesses in a statement) and only matches the most obvious cases, but seem to be enough to pattern-match Boost ublas gemm. Not handled cases include: - StoreInst instructions (a.k.a. explicit writes), since the value might be loaded or overwritten between the two stores. - PHINode, especially LCSSA, when the PHI value matches with on other's. - Partial writes (in preparation) llvm-svn: 302805
* [X86][AVX] Added zeroall/zeroupper scheduler testsSimon Pilgrim2017-05-111-0/+50
| | | | | | Missing on SandyBridge and Btver2 models llvm-svn: 302804
* Modules: fix modules build.Tim Northover2017-05-111-0/+1
| | | | | | | | A recent commit made GlobalVariable.h depend on intrinsics generation, so (I think) it needs to be in the lower-level module. I'll confirm with others, but this should fix the bots. llvm-svn: 302803
* Mark LWG#2782 as complete. No functionality change; we already do this. Just ↵Marshall Clow2017-05-112-2/+8
| | | | | | added a few more tests. llvm-svn: 302802
* Renumber test line number expectations after r302783.Benjamin Kramer2017-05-111-4/+3
| | | | | | Also remove a confused stable-runtimes requirement. llvm-svn: 302801
* Replace a nested namespace used for overload resolution with a struct. ↵Marshall Clow2017-05-111-2/+2
| | | | | | Richard Smith says that using the namespace results in an ODR violation, but I disagree. Nevertheless, the struct works just as well. llvm-svn: 302800
* Mark LWG#2850 as complete. No functionality change; we had tests that ↵Marshall Clow2017-05-112-2/+3
| | | | | | covered it already. Just added comments to the tests. Thanks to K-ballo for the heads up. llvm-svn: 302799
* Mark LWG#2796 as complete. No functionality change; we had tests that ↵Marshall Clow2017-05-113-2/+10
| | | | | | covered it already. Just added comments to the tests llvm-svn: 302798
* [CodeCompletion] Provide member completions for dependent expressions whoseAlex Lorenz2017-05-114-16/+126
| | | | | | | | | | | | | | type is a TemplateSpecializationType or InjectedClassNameType Fixes PR30847. Partially fixes PR20973 (first position only). PR17614 is still not working, its expression has the dependent builtin type. We'll have to teach the completion engine how to "resolve" dependent expressions to fix it. rdar://29818301 llvm-svn: 302797
* [CodeCompletion] NFC, extract a function that generates memberAlex Lorenz2017-05-111-30/+36
| | | | | | completion results for records llvm-svn: 302796
* Fix two-stage build on windows using DistributionExample cmake cacheNAKAMURA Takumi2017-05-112-6/+20
| | | | | | Thanks to Matthew Larionov <matthewtff@gmail.com> llvm-svn: 302795
* [IR] Allow attributes with global variablesJaved Absar2017-05-1112-9/+254
| | | | | | | | | | | | | This patch extends llvm-ir to allow attributes to be set on global variables. An RFC was sent out earlier by my colleague James Molloy: http://lists.llvm.org/pipermail/cfe-dev/2017-March/053100.html A key part of that proposal was to extend LLVM-IR to carry attributes on global variables. This generic feature could be useful for multiple purposes. In our present context, it would be useful to carry user specified sections for bss/rodata/data. Reviewed by: Jonathan Roelofs, Reid Kleckner Differential Revision: https://reviews.llvm.org/D32009 llvm-svn: 302794
* [GlobalISel][X86] Remove hand-written G_FADD/F_SUB selection.Igor Breger2017-05-111-105/+0
| | | | | | Now it handle by TableGen. llvm-svn: 302793
* [ELF] - Make text section location explicit in early-assign-symbol.s test.George Rimar2017-05-111-2/+2
| | | | | | | | Testcase itself depends on .text section location, which was orphan earlier. Suggested by Rafael Espíndola llvm-svn: 302792
* [X86] Moving X86Local namespace from .cpp to .h file to use it in memory ↵Ayman Musa2017-05-112-124/+123
| | | | | | | | folding TableGen backend. Differential Revision: https://reviews.llvm.org/D32797 llvm-svn: 302791
* [LV] Refactor ILV.vectorize{Loop}() by introducing LVP.executePlan(); NFCAyal Zaks2017-05-111-80/+101
| | | | | | | | | | | | | | Introduce LoopVectorizationPlanner.executePlan(), replacing ILV.vectorize() and refactoring ILV.vectorizeLoop(). Method collectDeadInstructions() is moved from ILV to LVP. These changes facilitate building VPlans and using them to generate code, following https://reviews.llvm.org/D28975 and its tentative breakdown. Method ILV.createEmptyLoop() is renamed ILV.createVectorizedLoopSkeleton() to improve clarity; it's contents remain intact. Differential Revision: https://reviews.llvm.org/D32200 llvm-svn: 302790
* [asan] Test 'strndup_oob_test.cc' added in r302781 fails on clang-s390x-linux.Pierre Gousseau2017-05-111-1/+1
| | | | | | Marking it as unsupported for now to hopefully make the bot green. llvm-svn: 302789
* [msan] add a regression test for PR32842Alexander Potapenko2017-05-111-0/+22
| | | | | | Make sure MSan doesn't miss a bug comparing two integers with defined low bits. llvm-svn: 302788
* [msan] Fix PR32842Alexander Potapenko2017-05-112-2/+25
| | | | | | | | | | | | | | | | | | | | It turned out that MSan was incorrectly calculating the shadow for int comparisons: it was done by truncating the result of (Shadow1 OR Shadow2) to i1, effectively rendering all bits except LSB useless. This approach doesn't work e.g. in the case where the values being compared are even (i.e. have the LSB of the shadow equal to zero). Instead, if CreateShadowCast() has to cast a bigger int to i1, we replace the truncation with an ICMP to 0. This patch doesn't affect the code generated for SPEC 2006 binaries, i.e. there's no performance impact. For the test case reported in PR32842 MSan with the patch generates a slightly more efficient code: orq %rcx, %rax jne .LBB0_6 , instead of: orl %ecx, %eax testb $1, %al jne .LBB0_6 llvm-svn: 302787
* [MSAN] test failed randomly on ARM when XFAILED for MIPSRenato Golin2017-05-111-0/+1
| | | | llvm-svn: 302786
* [x86] Fix a failure to select with AVX-512 when the type legalizerChandler Carruth2017-05-112-5/+90
| | | | | | | | | | | | | | | | | | | | | | | | | manages to form a VSELECT with a non-i1 element type condition. Those are technically allowed in SDAG (at least, the generic type legalization logic will form them and I wouldn't want to try to audit everything te preclude forming them) so we need to be able to lower them. This isn't too hard to implement. We mark VSELECT as custom so we get a chance in C++, add a fast path for i1 conditions to get directly handled by the patterns, and a fallback when we need to manually force the condition to be an i1 that uses the vptestm instruction to turn a non-mask into a mask. This, unsurprisingly, generates awful code. But it at least doesn't crash. This was actually impacting open source packages built with LLVM for AVX-512 in the wild, so quickly landing a patch that at least stops the immediate bleeding. I think I've found where to fix the codegen quality issue, but less confident of that change so separating it out from the thing that doesn't change the result of any existing test case but causes mine to not crash. llvm-svn: 302785
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-05-112-2/+2
| | | | llvm-svn: 302784
* mips] XFAIL wcsncpy.cc test.Simon Dardis2017-05-111-0/+2
| | | | | | | The stack unwinder fails to unwind the stack past the interceptor stack frame, resulting in a test failure. XFAIL this for now. llvm-svn: 302783
* [ARM][GlobalISel] Legalize narrow scalar ops by wideningDiana Picus2017-05-114-57/+218
| | | | | | | | | | | | | | This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB and MUL to 32 bits since we only have TableGen patterns for 32 bits. See the commit message for r292827 for more details. At this point we could just remove some of the tests for regbankselect and instruction-select, since we're not going to see any narrow operations at those levels anymore. Instead I decided to update them with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences generated by the legalizer. llvm-svn: 302782
* [asan] Recommit of r301904: Add strndup/__strndup interceptorsPierre Gousseau2017-05-1111-31/+158
| | | | | | | | | Fix undeclared __interceptor_malloc in esan_interceptors.cc Fix undeclared strnlen on OSX Differential Revision: https://reviews.llvm.org/D31457 llvm-svn: 302781
* Remove spurious cast of nullptr. NFC.Serge Guelton2017-05-115-6/+6
| | | | | | Conversion rules allow automatic casting of nullptr to any pointer type. llvm-svn: 302780
* Remove now useless trailing nullptr in StructType::getSerge Guelton2017-05-111-1/+1
| | | | llvm-svn: 302779
* [ARM][GlobalISel] Support for G_ANYEXTDiana Picus2017-05-114-10/+103
| | | | | | | | | | | | | | G_ANYEXT can be introduced by the legalizer when widening scalars. Add support for it in the register bank info (same mapping as everything else) and in the instruction selector. When selecting it, we treat it as a COPY, just like G_TRUNC. On this occasion we get rid of some assertions in selectCopy so we can reuse it. This shouldn't be a problem at the moment since we're not supporting any complicated cases (e.g. FPR, different register banks). We might want to separate the paths when we do. llvm-svn: 302778
* Reverted r302775Serge Pavlov2017-05-1115-57/+77
| | | | llvm-svn: 302777
* Revert "PR22877: When constructing an array via a constructor with a default ↵Diana Picus2017-05-112-50/+6
| | | | | | | | | | | | | | | | | | | | | | | argument in list-initialization, run cleanups for the default argument after each iteration of the initialization loop." Revert "clang/test/CodeGenCXX/array-default-argument.cpp: Satisfy targets that have x86_thiscallcc." This reverts commit r302750 and its fixup r302757 because the test is still breaking on some of the ARM bots. array-default-argument.cpp:20:12: error: expected string not found in input // CHECK: {{call|invoke}}[[THISCALL:( x86_thiscallcc)?]] void @_ZN1AC1Ev([[TEMPORARY:.*]]) ^ <stdin>:18:1: note: scanning from here arrayctor.loop: ; preds = %arrayctor.loop, %entry ^ <stdin>:28:2: note: possible intended match here call void @_Z1fv() ^ -- llvm-svn: 302776
* Driver must return non-zero code on errors in command lineSerge Pavlov2017-05-1115-77/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now if clang driver is given wrong arguments, in some cases it continues execution and returns zero code. This change fixes this behavior. The fix revealed some errors in clang test set. File test/Driver/gfortran.f90 added in r118203 checks forwarding gfortran flags to GCC. Now driver reports error on this file, because the option -working-directory implemented in clang differs from the option with the same name implemented in gfortran, in clang the option requires argument, in gfortran does not. In the file test/Driver/arm-darwin-builtin.c clang is called with options -fbuiltin-strcat and -fbuiltin-strcpy. These option were removed in r191435 and now clang reports error on this test. File arm-default-build-attributes.s uses option -verify, which is not supported by driver, it is cc1 option. Similarly, the file split-debug.h uses options -fmodules-embed-all-files and -fmodule-format=obj, which are not supported by driver. Other revealed errors are mainly mistypes. Differential Revision: https://reviews.llvm.org/D33013 llvm-svn: 302775
* [GlobalISel][X86] G_ICMP support.Igor Breger2017-05-116-5/+1090
| | | | | | | | | | | | | | Summary: support G_ICMP for scalar types i8/i16/i64. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits, krytarowski Differential Revision: https://reviews.llvm.org/D32995 llvm-svn: 302774
* Fix `std::visit` for the zero variants case.Michael Park2017-05-112-16/+17
| | | | | | | | | | | | | | | | | Summary: The following code is broken: ``` std::visit([]{}); ``` Reviewers: EricWF Reviewed By: EricWF Differential Revision: https://reviews.llvm.org/D33090 llvm-svn: 302773
* [APInt] Remove an unneeded extra temporary APInt from toString.Craig Topper2017-05-111-5/+1
| | | | | | Turns out udivrem can write its output to the same location as one of its inputs so the extra temporary isn't needed. llvm-svn: 302772
* Make tests from r302765 windows friendlyBruno Cardoso Lopes2017-05-113-9/+9
| | | | | | | and appease: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/2030 llvm-svn: 302771
* [APInt] Use negate() instead of copying an APInt to negate it and then ↵Craig Topper2017-05-111-3/+3
| | | | | | writing back over the original value. llvm-svn: 302770
* [SCEV] Reduce possible APInt allocations a bit.Craig Topper2017-05-111-7/+11
| | | | llvm-svn: 302769
* [SCEV] Remove unneeded 'using namespace APIntOps'.Craig Topper2017-05-111-37/+34
| | | | llvm-svn: 302768
* [X86] Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp. NFCIgor Breger2017-05-113-42/+46
| | | | | | | | | | | | | | | | Summary: Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp so it can be used by GloabalIsel instruction selector. This is a pre-commit for a patch I'm working on to support G_ICMP. NFC. Reviewers: zvi, guyblank, delena Reviewed By: guyblank, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33038 llvm-svn: 302767
* SupportTests: Suppress ParallelTests on mingw for now. Investigating.NAKAMURA Takumi2017-05-111-0/+5
| | | | llvm-svn: 302766
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