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* Add a TaskQueue that can serialize work on a ThreadPool.Zachary Turner2018-06-253-0/+243
| | | | | | | | | | | | We have ThreadPool, which can execute work asynchronously on N background threads, but sometimes you need to make sure the work is executed asynchronously but also serially. That is, if task B is enqueued after task A, then task B should not begin until task A has completed. This patch adds such a class. Differential Revision: https://reviews.llvm.org/D48240 llvm-svn: 335440
* [WebAssembly] Add WebAssemblyException information analysisHeejin Ahn2018-06-258-2/+939
| | | | | | | | | | | | | | | | | Summary: A WebAssemblyException object contains BBs that belong to a 'catch' part of the try-catch-end structure. Because CFGSort requires all the BBs within a catch part to be sorted together as it does for loops, this pass calculates the nesting structure of catch part of exceptions in a function. Now this assumes the use of Windows EH instructions. Reviewers: dschuff, majnemer Subscribers: jfb, mgorny, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44134 llvm-svn: 335439
* [WebAssembly] Add WebAssemblyLateEHPrepare passHeejin Ahn2018-06-256-98/+462
| | | | | | | | | | | | | | | | Summary: Add WebAssemblyLateEHPrepare pass that does several small jobs for exception handling. This runs before CFGSort, and is different from WasmEHPrepare pass that runs before ISel, even though the names are similar. Reviewers: dschuff, majnemer Subscribers: sbc100, jgravelle-google, sunfish, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46803 llvm-svn: 335438
* [X86] Simplify some code by using isOneConstant. NFCCraig Topper2018-06-251-2/+1
| | | | llvm-svn: 335437
* [X86] Remove the changes to combineScalarToVector made in r335037.Craig Topper2018-06-252-27/+6
| | | | | | They appear to be untested other than the test case for p37879.ll and I believe we should be using SimplifyDemandedElts here to handle these cases. llvm-svn: 335436
* [X86] Reduce the number of patterns needed for masked scalar ceil/floor isel.Craig Topper2018-06-251-35/+10
| | | | | | The scalar to vector on the mask register should not be part of the patterns. llvm-svn: 335435
* [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.Brad Smith2018-06-241-0/+5
| | | | | | | | Reviewers: atanasyan Differential Review: https://reviews.llvm.org/D31557 llvm-svn: 335434
* [DAGCombiner] eliminate setcc bool math when input is low-bit of some valueSanjay Patel2018-06-243-71/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has the same motivating example as D48466: define void @foo(i64 %x, i32 %c.0282.in, i32 %d.0280, i32* %ptr0, i32* %ptr1) { %c.0282 = and i32 %c.0282.in, 268435455 %a16 = lshr i64 32508, %x %a17 = and i64 %a16, 1 %tobool = icmp eq i64 %a17, 0 %. = select i1 %tobool, i32 1, i32 2 %.286 = select i1 %tobool, i32 27, i32 26 %shr97 = lshr i32 %c.0282, %. %shl98 = shl i32 %c.0282.in, %.286 %or99 = or i32 %shr97, %shl98 %shr100 = lshr i32 %d.0280, %. %shl101 = shl i32 %d.0280, %.286 %or102 = or i32 %shr100, %shl101 store i32 %or99, i32* %ptr0 store i32 %or102, i32* %ptr1 ret void } ...but I'm trying to kill the setcc bool math sooner rather than later. By matching a larger pattern that includes both the low-bit mask and the trailing add/sub, we can create a universally good fold because we always eliminate the condition code intermediate value. Here are Alive proofs for these (currently instcombine folds the 'add' variants, but misses the 'sub' patterns): https://rise4fun.com/Alive/Gsyp Name: sub of zext cmp mask %a = and i8 %x, 1 %c = icmp eq i8 %a, 0 %z = zext i1 %c to i32 %r = sub i32 C1, %z => %optional_cast = zext i8 %a to i32 %r = add i32 %optional_cast, C1-1 Name: add of zext cmp mask %a = and i32 %x, 1 %c = icmp eq i32 %a, 0 %z = zext i1 %c to i8 %r = add i8 %z, C1 => %optional_cast = trunc i32 %a to i8 %r = sub i8 C1+1, %optional_cast All of the tests look like improvements or neutral to me. But it is possible that x86 test+set+bitop is better than what we now show here. I suspect we could do better by adding another fold for the 'sub' variants. We start with select-of-constant in IR in the larger motivating test, so that's why I included tests with selects. Proofs for those variants: https://rise4fun.com/Alive/Bx1 Name: true const is bigger Pre: C2 == (C1 + 1) %a = and i8 %x, 1 %c = icmp eq i8 %a, 0 %r = select i1 %c, i64 C2, i64 C1 => %z = zext i8 %a to i64 %r = sub i64 C2, %z Name: false const is bigger Pre: C2 == (C1 + 1) %a = and i8 %x, 1 %c = icmp eq i8 %a, 0 %r = select i1 %c, i64 C1, i64 C2 => %z = zext i8 %a to i64 %r = add i64 C1, %z Differential Revision: https://reviews.llvm.org/D48466 llvm-svn: 335433
* [FileSpec] Always normalizeJonas Devlieghere2018-06-241-104/+6
| | | | | | | | Removing redundant components from the path seems pretty harmless. Rather than checking whether this is necessary and then actually doing so, always invoke remove_dots to start with a normalized path. llvm-svn: 335432
* Make testcase classnames uniqueJan Kratochvil2018-06-243-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Filenames with test results contain only the class name which makes it more difficult to find it if the same class name is present in multiple *.py files. packages/Python/lldbsuite/test/functionalities/step-avoids-no-debug/TestStepNoDebug.py -class ReturnValueTestCase(TestBase): +class StepAvoidsNoDebugTestCase(TestBase): as ReturnValueTestCase is already present in: packages/Python/lldbsuite/test/functionalities/return-value/TestReturnValue.py packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py -class CreateDuringStepTestCase(TestBase): +class CrashDuringStepTestCase(TestBase): as CreateDuringStepTestCase is already present in: packages/Python/lldbsuite/test/functionalities/thread/create_during_step/TestCreateDuringStep.py packages/Python/lldbsuite/test/functionalities/thread/step_until/TestStepUntil.py -class TestCStepping(TestBase): +class StepUntilTestCase(TestBase): as TestCStepping is already present in: packages/Python/lldbsuite/test/lang/c/stepping/TestStepAndBreakpoints.py llvm-svn: 335431
* [FileSpec] Refactor append and prepend implemenetations. NFCJonas Devlieghere2018-06-241-94/+20
| | | | | | | | Replaces custom implementations of append and prepend with calls to llvm's path library. This is part of a series of patches (started in D48084) to delegate common operations to llvm::sys::path. llvm-svn: 335430
* [X86] Regroup some isel patterns. NFCCraig Topper2018-06-241-32/+22
| | | | | | For some reason the 64-bit patterns were separated from their 8/16/32-bit friends, but only for add/sub/mul. For and/or/xor they were together. llvm-svn: 335429
* [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include ↵Craig Topper2018-06-243-14/+14
| | | | | | a Z to match other EVEX instructions. llvm-svn: 335428
* Also forward declare BitScanReverse.Zachary Turner2018-06-241-0/+2
| | | | | | | | | With the removal of intrin.h in an earlier patch, the intrinsics that we were actually using were manually re-declared, however several of them were missed leading to compilation failures with MSVC. Fix those. llvm-svn: 335427
* Add OpenBSD support to the Threading codeBrad Smith2018-06-231-3/+5
| | | | llvm-svn: 335426
* [CMake] Do not use --gc-sections on OpenBSDBrad Smith2018-06-231-1/+1
| | | | llvm-svn: 335425
* [CMake] Support building shared library for OpenBSDBrad Smith2018-06-231-0/+1
| | | | llvm-svn: 335424
* [llc] Fix sanitizer failure.Jonas Devlieghere2018-06-231-1/+1
| | | | | | | | | | | Store the string on the stack rather than just the StringRef. Fix sanitizer bots: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19948 http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/5500 llvm-svn: 335423
* [Coroutines] Less IR for noexcept await_resumeBrian Gesiak2018-06-232-14/+64
| | | | | | | | | | | | | | | | | | | | Summary: In his review of https://reviews.llvm.org/D45860, @GorNishanov suggested avoiding generating additional exception-handling IR in the case that the resume function was marked as 'noexcept', and exceptions could not occur. This implements that suggestion. Test Plan: `check-clang` Reviewers: GorNishanov, EricWF Reviewed By: GorNishanov Subscribers: cfe-commits, GorNishanov Differential Revision: https://reviews.llvm.org/D47673 llvm-svn: 335422
* ADT: Use EBO to shrink SmallVector size 1Duncan P. N. Exon Smith2018-06-232-4/+5
| | | | | | | SmallVectorStorage is empty when its size is 1; use inheritance so that the empty base class optimization kicks in. llvm-svn: 335421
* [Sema] isValidCoroutineContext FIXME and citationsBrian Gesiak2018-06-232-2/+40
| | | | | | | | | | | | | | | | | | | Summary: Add citations to the Coroutines TS to the `isValidCoroutineContext` function, as well as a FIXME and test for [expr.await]p2, which states a co_await expression cannot be used in a default argument. Test Plan: check-clang Reviewers: GorNishanov, EricWF Reviewed By: GorNishanov Subscribers: rsmith, cfe-commits Differential Revision: https://reviews.llvm.org/D48519 llvm-svn: 335420
* Attempt to fix latent tablegen dependency issueReid Kleckner2018-06-231-1/+10
| | | | llvm-svn: 335419
* [llc] Use WithColor for printing errors/warningsJonas Devlieghere2018-06-231-19/+27
| | | | | | Use the WithColor helper from support to print errors and warnings. llvm-svn: 335418
* [llvm-config] Use WithColor for printing errors.Jonas Devlieghere2018-06-231-7/+9
| | | | | | Use the WithColor helper from support to print errors. llvm-svn: 335417
* [llvm-mt] Use WithColor for printing errors.Jonas Devlieghere2018-06-234-6/+7
| | | | | | Use the WithColor helper from support to print errors. llvm-svn: 335416
* [TableGen] Use WithColor for printing errors/warningsJonas Devlieghere2018-06-231-6/+3
| | | | | | Use the WithColor helper from support to print errors and warnings. llvm-svn: 335415
* [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix ↵Craig Topper2018-06-232-6/+12
| | | | | | some test CHECK lines. llvm-svn: 335414
* [X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is ↵Craig Topper2018-06-232-1/+7
| | | | | | used on a rip-relative address. llvm-svn: 335413
* [X86][AsmParser] Improve base/index register checks.Craig Topper2018-06-232-8/+45
| | | | | | | | | -Ensure EIP isn't used with an index reigster. -Ensure EIP isn't used as index register. -Ensure base register isn't a vector register. -Ensure eiz/riz usage matches the size of their base register. llvm-svn: 335412
* Fix invariant fdiv hoisting in LICMStanislav Mekhanoshin2018-06-232-16/+42
| | | | | | | | | | | | | FDiv is replaced with multiplication by reciprocal and invariant reciprocal is hoisted out of the loop, while multiplication remains even if invariant. Switch checks for all invariant operands and only invariant denominator to fix the issue. Differential Revision: https://reviews.llvm.org/D48447 llvm-svn: 335411
* [Fuchsia] Enable static libc++, libc++abi, libunwindPetr Hosek2018-06-233-6/+10
| | | | | | | | This is needed for building Fuchsia drivers. Differential Revision: https://reviews.llvm.org/D48208 llvm-svn: 335410
* [AMDGPU] Update includes for intrinsic changes :(Reid Kleckner2018-06-232-4/+4
| | | | llvm-svn: 335409
* [ORC] Fix formatting and list pending queries in VSO::dump.Lang Hames2018-06-231-3/+7
| | | | llvm-svn: 335408
* [IR] Split Intrinsics.inc into enums and implementationsReid Kleckner2018-06-2310-43/+68
| | | | | | | | | | | | | | | | | | | Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
* Avoid including intrin.h from MathExtras.hReid Kleckner2018-06-231-4/+10
| | | | | | | | This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a very popular header, and it basically pulls all Intel intrinsics into every LLVM TU. Let's not do that. llvm-svn: 335406
* [ELF] Change isSectionData to exclude SHF_EXECINSTRFangrui Song2018-06-232-3/+4
| | | | | | | | | | | | | | | | | | | Summary: This affects what sections are displayed as "DATA" in llvm-objdump. The other user llvm-size is unaffected. Before, a "TEXT" section is also "DATA", which seems weird. The sh_flags condition matches that of bfd's SEC_DATA but the sh_type condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS). bfd's SEC_DATA is not appealing as so many sections will be shown as DATA. Reviewers: jyknight, Bigcheese Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48472 llvm-svn: 335405
* [ELF] Change llvm-objdump output for D48472: TEXT DATA -> TEXTFangrui Song2018-06-2315-25/+25
| | | | | | | | | | Reviewers: jyknight, Bigcheese, espindola Subscribers: emaste, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D48473 llvm-svn: 335404
* [X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with ↵Craig Topper2018-06-231-41/+29
| | | | | | | | | | in/out instructions. Previously, to support (%dx) we left a wide open hole in our 16-bit memory address checking. This let this address value be used with any instruction without error in the parser. It would later fail in the encoder with an assertion failure on debug builds and who knows what on release builds. This patch passes the mnemonic down to the memory operand parsing function so we can allow the (%dx) form only on specific instructions. llvm-svn: 335403
* [RuntimeDyld] Implement the ELF PIC large code model relocationsReid Kleckner2018-06-222-0/+147
| | | | | | | Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF large PIC codegen. llvm-svn: 335402
* Update cmdtemplate.py to use best pratices.Greg Clayton2018-06-221-53/+78
| | | | | | | | | | Fixes include: - fix all lint errors - add code that will automatically register and LLDB command classes by detecting the classes and any classes that have a "register_lldb_command" function - automatically fill in the correct module name when registering commands - automatically fill in the class name when registering command llvm-svn: 335401
* [LoopReroll] Rewrite induction variable rewriting.Eli Friedman2018-06-227-253/+179
| | | | | | | | | | | | | | | | | | | | This gets rid of a bunch of weird special cases; instead, just use SCEV rewriting for everything. In addition to being simpler, this fixes a bug where we would use the wrong stride in certain edge cases. The one bit I'm not quite sure about is the trip count handling, specifically the FIXME about overflow. In general, I think we need to widen the exit condition, but that's probably not profitable if the new type isn't legal, so we probably need a check somewhere. That said, I don't think I'm making the existing problem any worse. As a followup to this, a bunch of IV-related code in root-finding could be cleaned up; with SCEV-based rewriting, there isn't any reason to assume a loop will have exactly one or two PHI nodes. Differential Revision: https://reviews.llvm.org/D45191 llvm-svn: 335400
* [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFCGeorge Burgess IV2018-06-221-6/+5
| | | | llvm-svn: 335399
* [X86][AsmParser] Keep track of whether an explicit scale was specified while ↵Craig Topper2018-06-222-8/+22
| | | | | | | | | | parsing an address in Intel syntax. Use it for improved error checking. This allows us to check these: -16-bit addressing doesn't support scale so we should error if we find one there. -Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP can't be an index. llvm-svn: 335398
* [llvm-size] Make global variables staticFangrui Song2018-06-221-2/+2
| | | | llvm-svn: 335397
* [x86] add more tests for bit hacking opportunities with setcc; NFCSanjay Patel2018-06-221-0/+56
| | | | | | Missed cases where the input and output are the same size in rL335391. llvm-svn: 335396
* [PowerPC] add more tests for bit hacking opportunities with setcc; NFCSanjay Patel2018-06-221-0/+57
| | | | | | Missed cases where the input and output are the same size in rL335390. llvm-svn: 335395
* [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the ↵Craig Topper2018-06-222-0/+12
| | | | | | | | | | second register in memory expressions like [EAX+ESP]. By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register. There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently. llvm-svn: 335394
* [Sema] -Wformat-pedantic only for NSInteger/NSUInteger %zu/%zi on DarwinJF Bastien2018-06-227-40/+109
| | | | | | | | | | | | | | | | | | | | | | | Summary: Pick D42933 back up, and make NSInteger/NSUInteger with %zu/%zi specifiers on Darwin warn only in pedantic mode. The default -Wformat recently started warning for the following code because of the added support for analysis for the '%zi' specifier. NSInteger i = NSIntegerMax; NSLog(@"max NSInteger = %zi", i); The problem is that on armv7 %zi is 'long', and NSInteger is typedefed to 'int' in Foundation. We should avoid this warning as it's inconvenient to our users: it's target specific (happens only on armv7 and not arm64), and breaks their existing code. We should also silence the warning for the '%zu' specifier to ensure consistency. This is acceptable because Darwin guarantees that, despite the unfortunate choice of typedef, sizeof(size_t) == sizeof(NS[U]Integer), the warning is therefore noisy for pedantic reasons. Once this is in I'll update public documentation. Related discussion on cfe-dev: http://lists.llvm.org/pipermail/cfe-dev/2018-May/058050.html <rdar://36874921&40501559> Reviewers: ahatanak, vsapsai, alexshap, aaron.ballman, javed.absar, jfb, rjmccall Subscribers: kristof.beyls, aheejin, cfe-commits Differential Revision: https://reviews.llvm.org/D47290 llvm-svn: 335393
* [llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.Matt Davis2018-06-222-5/+3
| | | | | | | The DispatchUnit is no longer a dependency of RCU, so this patch removes a stale include and forward decl. This patch also cleans up some comments. llvm-svn: 335392
* [x86] add tests for bit hacking opportunities with setcc; NFCSanjay Patel2018-06-221-0/+117
| | | | | | | | | | We likely gave up on folding some select-of-constants patterns in IR with rL331486, and we need to recover those in the DAG. The tests without select are based on our current DAGCombiner optimizations for select-of-constants. llvm-svn: 335391
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