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* Make test pass in Release builds, which use a different naming scheme for ↵Benjamin Kramer2012-08-281-1/+1
| | | | | | llvm values. llvm-svn: 162771
* Don't allow TargetFlags on MO_Register MachineOperands.Jakob Stoklund Olesen2012-08-282-10/+21
| | | | | | | | | | | | Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. llvm-svn: 162770
* Merge test case for PR13704 into exprs.c to reduce test casesMichael Liao2012-08-282-9/+10
| | | | llvm-svn: 162769
* [ms-inline asm] Make the AsmStmt class non-virtual.Chad Rosier2012-08-282-9/+61
| | | | llvm-svn: 162768
* Patch by Sean Silva to un-barf his computer by explicitly removing the '\n'Bill Wendling2012-08-281-3/+2
| | | | | | character instead of always the last character. llvm-svn: 162767
* Fix PR13704Michael Liao2012-08-282-1/+10
| | | | | | | - The increment needs to be signed value to preserve the original value when its data type is larger than 64-bit integer. llvm-svn: 162766
* Fix passing of -analyzer-max-loop from scan-build to clang.Ted Kremenek2012-08-281-1/+1
| | | | llvm-svn: 162765
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-2810-2/+653
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* Warn about suspicious implicit conversions from floating point to boolHans Wennborg2012-08-284-0/+93
| | | | | | | | | | | | | | | | | | | | | This warns in two specific situations: 1) For potentially swapped function arguments, e.g. void foo(bool, float); foo(1.7, false); 2) Misplaced brackets around function call arguments, e.g. bool InRange = fabs(a - b < delta); Where the last argument in a function call is implicitly converted from bool to float, and the function returns a float which gets implicitly converted to bool. Patch by Andreas Eckleder! llvm-svn: 162763
* [asan] one more fix for windows buildKostya Serebryany2012-08-282-5/+2
| | | | llvm-svn: 162762
* Cleanup FreeBSD linking and add support for -pie.Roman Divacky2012-08-282-32/+62
| | | | | | Path by Brooks Davis, tests and fixes from me. llvm-svn: 162761
* [asan] fix the cmake build (hopefully)Kostya Serebryany2012-08-282-7/+7
| | | | llvm-svn: 162760
* [asan] actually doing 'svn add' helpsKostya Serebryany2012-08-282-0/+298
| | | | llvm-svn: 162759
* [asan] fix Windows buildKostya Serebryany2012-08-281-7/+7
| | | | llvm-svn: 162758
* [asan] actually move StackTrace to sanitizer_commonKostya Serebryany2012-08-285-272/+16
| | | | llvm-svn: 162757
* Fixes by Daniel Malea.Filipe Cabecinhas2012-08-282-2/+3
| | | | llvm-svn: 162756
* InstCombine: Defensively avoid undefined shifts by limiting the amount to ↵Benjamin Kramer2012-08-281-2/+2
| | | | | | | | | the bit width. No test case, undefined shifts get folded early, but can occur when other transforms generate a constant. Thanks to Duncan for bringing this up. llvm-svn: 162755
* [asan] even more refactoring to move StackTrace to sanitizer_commonKostya Serebryany2012-08-285-36/+45
| | | | llvm-svn: 162754
* Simplify the typecheck code.Filipe Cabecinhas2012-08-281-10/+4
| | | | llvm-svn: 162753
* [asan] more refactoring to move StackTrace to sanitizer_commonKostya Serebryany2012-08-284-27/+26
| | | | llvm-svn: 162752
* InstCombine: Guard the transform introduced in r162743 against large ints ↵Benjamin Kramer2012-08-282-12/+37
| | | | | | and non-const shifts. llvm-svn: 162751
* [ASan] CMake build: share more compile flags between instrumented and ↵Alexey Samsonov2012-08-281-6/+7
| | | | | | non-instrumented tests llvm-svn: 162750
* Make sure that we don't call getZExtValue on values > 64 bits.Nadav Rotem2012-08-282-8/+15
| | | | | | Thanks Benjamin for noticing this. llvm-svn: 162749
* [asan] some renaming before we move StackTrace into sanitizer_common (part 2)Kostya Serebryany2012-08-281-0/+2
| | | | llvm-svn: 162748
* [asan] some renaming before we move StackTrace into sanitizer_commonKostya Serebryany2012-08-2813-87/+83
| | | | llvm-svn: 162747
* [asan] get rid of AsanPrintf in favor of Printf from sanitizer_commonKostya Serebryany2012-08-2812-131/+80
| | | | llvm-svn: 162746
* [asan] improve SetErrorReportCallbackTest to actually catch missing ↵Kostya Serebryany2012-08-282-2/+7
| | | | | | functionality in __asan_set_error_report_callback llvm-svn: 162745
* Check for MIPS target availability for Driver/mips-as.c test.Simon Atanasyan2012-08-281-0/+2
| | | | llvm-svn: 162744
* Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.Nadav Rotem2012-08-283-2/+72
| | | | | | | | | | For example: %1 = lshr i32 %x, 2 %2 = udiv i32 %1, 100 rdar://12182093 llvm-svn: 162743
* [Sanitizer] Allow to create stub MemoryMappingLayout on WindowsAlexey Samsonov2012-08-281-3/+1
| | | | llvm-svn: 162742
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-282-1/+21
| | | | | | | | it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> llvm-svn: 162741
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-283-18/+10
| | | | llvm-svn: 162740
* [Sanitizer] One more method stub for WindowsAlexey Samsonov2012-08-281-4/+8
| | | | llvm-svn: 162739
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-284-32/+19
| | | | llvm-svn: 162738
* Fix for assertion when solving unresolved templates.Rafael Espindola2012-08-282-1/+23
| | | | | | Patch by Magee, Josh. llvm-svn: 162737
* llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2012-08-281-2/+2
| | | | llvm-svn: 162736
* Fix PR12312Michael Liao2012-08-282-10/+160
| | | | | | | | | | - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735
* Check all patterns for missing instruction flags.Jakob Stoklund Olesen2012-08-282-0/+72
| | | | | | | Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. llvm-svn: 162734
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-285-31/+25
| | | | | | | | | | | | | | | These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. llvm-svn: 162733
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-286-169/+43
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Fix mips' long branch pass.Akira Hatanaka2012-08-283-109/+141
| | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. llvm-svn: 162731
* Fix a -Wdocumentation warning.Dmitri Gribenko2012-08-281-3/+3
| | | | llvm-svn: 162730
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Fix bug 13532.Akira Hatanaka2012-08-282-1/+13
| | | | | | | | | In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. llvm-svn: 162728
* Allow remat of LI on PPC.Hal Finkel2012-08-284-3/+21
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Add the Freescale vendor to Triple.Hal Finkel2012-08-282-1/+4
| | | | | | | | | Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow clang support for Freescale cross-compile configurations. Patch by Tobias von Koch. llvm-svn: 162726
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-284-8/+60
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-282-0/+20
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* Merging consecutive comments: be more conservative.Dmitri Gribenko2012-08-282-16/+21
| | | | | | Should fix part 2 of PR13374. llvm-svn: 162723
* Temporarily revert this to bring back the bots.Eric Christopher2012-08-284-21/+15
| | | | llvm-svn: 162722
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