| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 118176
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For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
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Makes it more clear that it is just a path manipulation function.
llvm-svn: 118174
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llvm-svn: 118173
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llvm-svn: 118172
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the code more self-documenting.
llvm-svn: 118171
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libclang with both clang -fblocks and gcc (no blocks support). Only exposed in
the header to compilers that do have blocks support.
llvm-svn: 118170
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
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llvm-svn: 118168
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
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llvm-svn: 118166
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llvm-svn: 118165
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this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
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llvm-svn: 118163
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extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
llvm-svn: 118160
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that are not handled properly:
1. For statement: const C& c = C(0) ?: C(1) destructors generated for condition will not differ from those generated for case without prolonged lifetime of temporary,
2. There will be no destructor for constant reference member bound to temporary at the exit from constructor.
llvm-svn: 118158
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llvm-svn: 118152
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llvm-svn: 118151
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llvm-svn: 118150
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distros listed by running
gcc main.o -o main
g++ main.o -o main
gcc main.o -o main -static
g++ main.o -o main -static
gcc f.o -o f.so -shared
g++ f.o -o f.so -shared
and comparing the ld line with the one created by clang. I also added
-m32/m64 in distros that support it.
While I tested many distros, there will always be more. If you are hit by this
it should be somewhat easy to add your distro. If you are in a hurry, do
revert this, but please inform how to detect you distro and the ld command
lines produced by the above gcc invocations. Most distros have some patches
on gcc :-(
llvm-svn: 118149
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easier to read.
llvm-svn: 118148
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the end of the list. We had an issue in the MacOSX dynamic loader where if
we had shlibs:
1 - a.out
2 - a.dylib
3 - b.dylib
And then a.dylib got unloaded, we would unload b.dylib due to the assumption
that only shared libraries could come off the end of the list. We now properly
search and find which ones get loaded.
Added a new internal logging category for the "lldb" log channel named "dyld".
This should allow all dynamic loaders to use this as a generic log channel so
we can track shared library loads and unloads in the logs without having to
have each plug-in make up its own logging channel.
llvm-svn: 118147
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constraint it's invalid. Fixes PR3905.
llvm-svn: 118146
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constraint. Fixes PR3904.
llvm-svn: 118145
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
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encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
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set breakpoints at the different locations where
an exception could be thrown, so that exceptions
thrown by expressions are properly caught.
llvm-svn: 118142
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llvm-svn: 118141
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
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llvm-svn: 118139
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parameter name.
Fixes PR8012.
llvm-svn: 118138
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
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latencies) of loads.
llvm-svn: 118134
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llvm-svn: 118133
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ensuring that they cover all of their child nodes. There's still a
clang_getCursor()-related issue with CXXFunctionalCastExprs with
CXXConstructExprs as children (see FIXME in the test case); I'll look
at that separately.
llvm-svn: 118132
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llvm-svn: 118131
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llvm-svn: 118130
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llvm-svn: 118129
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llvm-svn: 118128
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llvm-svn: 118127
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llvm-svn: 118126
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instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
llvm-svn: 118125
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llvm-svn: 118124
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for a global variable that we had replaced with
a reference to a slot in the input array.
llvm-svn: 118123
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llvm-svn: 118122
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llvm-svn: 118121
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llvm-svn: 118120
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
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clang are using.
llvm-svn: 118118
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