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* NVPTX: Rename __builtin_ptx_shfl -> __nvvm_shflJustin Bogner2016-07-062-16/+12
| | | | | | | To match "NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names consistent" in LLVM. llvm-svn: 274663
* NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names consistentJustin Bogner2016-07-062-24/+24
| | | | | | | The intrinsics here use nvvm, but the builtins and tablegen variable names were using ptx. Stick to the modern names here. llvm-svn: 274662
* Retry: "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-063-7/+127
| | | | | | | | | | Now with a corrected test to account for a recently supported properties bit in the debug info of a struct. Original review: http://reviews.llvm.org/D21939 This reverts commit 970c3fd497a28d25dd69526eb52594a696c37968. llvm-svn: 274661
* [DSE] Avoid iterator invalidation bugs.Chad Rosier2016-07-062-123/+34
| | | | | | | | | | The dse_with_dbg_value.ll test committed with r273141 is removed because this we no longer performs any type of back tracking, which is what was causing the codegen differences with and without debug information. Differential Revision: http://reviews.llvm.org/D21613 llvm-svn: 274660
* [Conduct] Refine what "rare cases" means wrt violations outside our spaces.Paul Robinson2016-07-061-1/+2
| | | | | | | | | | Text suggested by Daniel Berlin. While it is likely to be exactly what the advisory committee would do anyway, codifying it does no harm and helps reassure people that rare does not mean arbitrary. Differential Revision: http://reviews.llvm.org/D21981 llvm-svn: 274659
* [x86] fix cost of SINT_TO_FP for i32 --> float (PR21356, PR28434)Sanjay Patel2016-07-062-7/+7
| | | | | | | | | | | | | This is "cvtdq2ps" which does not appear to be particularly slow on any CPU according to Agner's tables. Choosing "5" as a cost here as suggested in: https://llvm.org/bugs/show_bug.cgi?id=21356 ...but it seems very conservative given that the instruction is fully pipelined, and I think these costs are supposed to model throughput. Note that related costs are also most likely too high, but this fixes PR21356 and partly fixes PR28434. llvm-svn: 274658
* [compilter-rt] Add unittests for interception libraryEtienne Bergeron2016-07-066-1/+382
| | | | | | | | | | | | | | Summary: This patch is adding unittests for the interception library. Reviewers: rnk Subscribers: majnemer, llvm-commits, wang0109, chrisha, tberghammer, danalbert, srhines Differential Revision: http://reviews.llvm.org/D21980 llvm-svn: 274657
* Work around PR28400 a bit harder.Sean Silva2016-07-062-2/+24
| | | | | | | | | | We were still crashing in the "no change" case because LVI was not getting invalidated. See the thread "Should analyses be able to hold AssertingVH to IR? (related to PR28400)" for more discussion. llvm-svn: 274656
* TailDuplicator: Remove live-in updating logicMatthias Braun2016-07-062-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This logic was introduced in r157663 and does not make any sense to me. The motivating example in rdar://11538365 looks like this: This is the tail: BB#16: derived from LLVM BB %if.end68 Live Ins: %R0 %R4 %R5 Predecessors according to CFG: BB#15 BB#5 tBLXi pred:14, pred:%noreg, <ga:@CFRelease>, %R0<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %SP<imp-def> t2B <BB#20>, pred:14, pred:%noreg Successors according to CFG: BB#20 This is the predBB: BB#5: Live Ins: %R5 Predecessors according to CFG: BB#4 %R4<def> = t2MOVi 0, pred:14, pred:%noreg, opt:%noreg t2B <BB#16>, pred:14, pred:%noreg Successors according to CFG: BB#16 However this is invalid machine code to begin with, if %R0 is live-in to BB#16 then it must be live-in to BB#5 as well if BB#5 does not define it. We should not need logic to retroactively fix broken machine code and in fact the example from r157663 passes cleanly with the code removed and I do not see any (newly) failing tests with the machine verifier enabled. Differential Revision: http://reviews.llvm.org/D22031 llvm-svn: 274655
* Ensuring the bit-fields have the same type; MSVC will place the fields in ↵Aaron Ballman2016-07-061-1/+1
| | | | | | different allocation units otherwise. llvm-svn: 274654
* [X86] Sort cast cost tables. NFC.Michael Kuperstein2016-07-061-124/+123
| | | | | | | Cast cost tables are now sorted, for each cast type, lexicographically on [source base type, source vector width, dest base type, base vector width]. llvm-svn: 274653
* Add AST matchers for handling bit-fields and narrowing based on their width.Aaron Ballman2016-07-064-1/+70
| | | | llvm-svn: 274652
* Revert r274605 due to bot failure: ↵Manman Ren2016-07-061-7/+7
| | | | | | http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/244/ llvm-svn: 274651
* [SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotateElliot Colp2016-07-065-3/+249
| | | | | | | | | | On SystemZ, shift and rotate instructions only use the bottom 6 bits of the shift/rotate amount. Therefore, if the amount is ANDed with an immediate mask that has all of the bottom 6 bits set, we can remove the AND operation entirely. Differential Revision: http://reviews.llvm.org/D21854 llvm-svn: 274650
* NFC changed names in FunctionImportPiotr Padlewski2016-07-061-14/+14
| | | | llvm-svn: 274649
* [X86][SSE] Fixed typo in insertps lowering.Simon Pilgrim2016-07-061-1/+1
| | | | | | | | We were checking for 2 insertions (which is caught earlier in the pattern matching loop) instead of the case where we have no insertions. Turns out this code never fires as we always try to lower to insertps after trying to lower to blendps, which would catch these cases - I'm about to make some changes to support combining to insertps which could cause this to fire so I don't want to remove it. llvm-svn: 274648
* [pdb] Round trip the PDB stream between YAML and binary PDB.Zachary Turner2016-07-0624-28/+377
| | | | | | This gets writing of the PDB stream working. llvm-svn: 274647
* [SemaExpr] Support assignments from vector to scalars with same sizeBruno Cardoso Lopes2016-07-062-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before r266366, clang used to support constructs like: typedef __attribute__((vector_size(8))) double float64x1_t; typedef __attribute__((vector_size(16))) double float64x2_t; float64x1_t vget_low_f64(float64x2_t __p0); double y = 3.0 + vget_low_f64(v); But it would reject: double y = vget_low_f64(v) + 3.0; It also always rejected assignments: double y = vget_low_f64(v); This patch: (a) revivies the behavior of `3.0 + vget_low_f64(v)` prior to r266366, (b) add support for `vget_low_f64(v) + 3.0` and (c) add support for assignments. These vector semantics have never really been tied up but it seems odd that we used to support some binop froms but do not support assignment. If we did support scalar for the purposes of arithmetic, we should probably be able to reinterpret as scalar for the purposes of assignment too. Differential Revision: http://reviews.llvm.org/D21700 rdar://problem/26093791 llvm-svn: 274646
* Ensure all uses of permute instructions feed vector storesKit Barton2016-07-062-0/+75
| | | | | | | | | | | | | | | There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
* [DAGCombiner] Fix visitSTORE to continue processing current SDNode, if ↵Tim Shen2016-07-062-6/+82
| | | | | | | | | | | | | | | | | findBetterNeighborChains doesn't actually CombineTo it. Summary: findBetterNeighborChains may or may not find a better chain for each node it finds, which include the node ("St") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed. This fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase. Reviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner Subscribers: mehdi_amini, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D21692 llvm-svn: 274644
* [gardening] Switch back to auto. NFCI.Davide Italiano2016-07-061-3/+1
| | | | | | Pointed out by: Rui Ueyama. llvm-svn: 274643
* [TTI] The cost model should not assume vector casts get completely scalarizedMichael Kuperstein2016-07-067-221/+241
| | | | | | | | | | | | | | | | The cost model should not assume vector casts get completely scalarized, since on targets that have vector support, the common case is a partial split up to the legal vector size. So, when a vector cast gets split, the resulting casts end up legal and cheap. Instead of pessimistically assuming scalarization, base TTI can use the costs the concrete TTI provides for the split vector, plus a fudge factor to account for the cost of the split itself. This fudge factor is currently 1 by default, except on AMDGPU where inserts and extracts are considered free. Differential Revision: http://reviews.llvm.org/D21251 llvm-svn: 274642
* Fix the nowait tests for omp for and omp singleJonathan Peyton2016-07-062-48/+88
| | | | | | | | | | These tests are now modeled after the sections nowait test where threads wait to be released in the first construct (either for or single) and the last thread skips the last for/single construct and releases those threads. If the test fails, then it hangs because an unnecessary barrier is executed in between the constructs. llvm-svn: 274641
* Add a default parameter for getRegisteredOptions.Zachary Turner2016-07-061-1/+1
| | | | llvm-svn: 274640
* Disable hash verification of enums.Zachary Turner2016-07-062-1/+3
| | | | llvm-svn: 274639
* Fix ADB client disconnect issues.Oleksiy Vyalov2016-07-064-25/+106
| | | | | | http://reviews.llvm.org/D22029 llvm-svn: 274638
* Prune RelocVisitor.h include to avoid including COFF.h from MCJIT.hReid Kleckner2016-07-065-1/+7
| | | | | | | This helps to mitigate the conflict between COFF.h and winnt.h, which is PR28399. llvm-svn: 274637
* fix typo; NFCSanjay Patel2016-07-061-1/+1
| | | | llvm-svn: 274636
* Add oat symbolization support for odex filesTamas Berghammer2016-07-062-6/+8
| | | | | | Differential revision: http://reviews.llvm.org/D22040 llvm-svn: 274635
* [asan Win64] Implement atomic_compare_exchange_strong for 8 bitEtienne Bergeron2016-07-061-7/+9
| | | | | | | Patch by: Wei Wang Differential Revision: http://reviews.llvm.org/D21950 llvm-svn: 274634
* Revert "Include debug info for nested structs and classes"Adrian McCarthy2016-07-065-24/+12
| | | | | | This reverts commit 0af5ee9631c7c167dc40498b415876553e314c95. llvm-svn: 274633
* Revert "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-063-127/+7
| | | | | | This reverts commit 256b29322c827a2d94da56468c936596f5509032. llvm-svn: 274632
* [X86][SSE] Added test cases for missed opportunities to combine pshufb to ↵Simon Pilgrim2016-07-063-0/+82
| | | | | | pslldq/psrldq llvm-svn: 274631
* Emit CodeView type records for nested classes.Adrian McCarthy2016-07-063-7/+127
| | | | | | Differential Revision: http://reviews.llvm.org/D21939 llvm-svn: 274629
* Include debug info for nested structs and classesAdrian McCarthy2016-07-065-12/+24
| | | | | | | | This includes nested types in the member list, even if there are no members of that type. Note that structs and classes have themselves as an "implicit struct" as the first member, so we skip implicit ones. Differential Revision: http://reviews.llvm.org/D21705 llvm-svn: 274628
* [LV] Don't widen trivial induction variablesMatthew Simpson2016-07-065-24/+256
| | | | | | | | | | | | | | | | | | | | We currently always vectorize induction variables. However, if an induction variable is only used for counting loop iterations or computing addresses with getelementptr instructions, we don't need to do this. Vectorizing these trivial induction variables can create vector code that is difficult to simplify later on. This is especially true when the unroll factor is greater than one, and we create vector arithmetic when computing step vectors. With this patch, we check if an induction variable is only used for counting iterations or computing addresses, and if so, scalarize the arithmetic when computing step vectors instead. This allows for greater simplification. This patch addresses the suboptimal pointer arithmetic sequence seen in PR27881. Reference: https://llvm.org/bugs/show_bug.cgi?id=27881 Differential Revision: http://reviews.llvm.org/D21620 llvm-svn: 274627
* Re-commit of 274613.Elena Demikhovsky2016-07-0613-329/+379
| | | | | | | The prev commit failed on compilation. A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure. llvm-svn: 274626
* [LLGS] Log more precise errors during inferior launchPavel Labath2016-07-062-113/+129
| | | | | | | | | | | | | | Summary: We are seeing infrequent failures to launch the inferior process on android. The failing call seems to be execve(). This adds more logging to see the actual error reported by the call. Reviewers: tberghammer Subscribers: tberghammer, lldb-commits, danalbert Differential Revision: http://reviews.llvm.org/D22039 llvm-svn: 274624
* [AMDGPU] Assembler: regression tests for bug 28413. NFCSam Kolton2016-07-063-10/+36
| | | | llvm-svn: 274623
* Use / instead of \ on windows created cpio filesRafael Espindola2016-07-062-2/+9
| | | | | | | Otherwise when extracting these files on a unix system one ends up with files named like "repro\bar\foo.o". llvm-svn: 274622
* In AddressSanitizer and ThreadSanitizer, let's explicitly set the language ↵Kuba Brecka2016-07-063-0/+5
| | | | | | of the expression we're evaluating. llvm-svn: 274621
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-065-15/+21
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* [tsan] Fix false positives with GCD dispatch_source_*Kuba Brecka2016-07-062-24/+77
| | | | | | | | We already have interceptors for dispatch_source API (e.g. dispatch_source_set_event_handler), but they currently only handle submission synchronization. We also need to synchronize based on the target queue (serial, concurrent), in other words, we need to use dispatch_callback_wrap. This patch implements that. Differential Revision: http://reviews.llvm.org/D21999 llvm-svn: 274619
* Add data formatter for libstdc++ shared_ptr and weak_ptrTamas Berghammer2016-07-067-25/+236
| | | | | | Differential revision: http://reviews.llvm.org/D21984 llvm-svn: 274617
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCIDiana Picus2016-07-065-7/+40
| | | | | | | | | | | This is a follow-up for r273544 and r273853. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also marks them as obsolete. Differential Revision: http://reviews.llvm.org/D21796 llvm-svn: 274616
* Reverted 274613 due to compilation failue. Elena Demikhovsky2016-07-0613-379/+329
| | | | llvm-svn: 274615
* isl: isl-0.17.1-164-gcbba1b6Tobias Grosser2016-07-0643-708/+1455
| | | | | | | | | | | This is a regular maintenance update to ensure the latest version of isl is tested. Interesting Changes: - AST nodes and expressions are now printed as YAML llvm-svn: 274614
* AVX-512: Optimization for patterns with i1 scalar typeElena Demikhovsky2016-07-0613-329/+379
| | | | | | | | | | | | | | The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc". I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction. I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions. This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173. Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails). Differential revision: http://reviews.llvm.org/D21956 llvm-svn: 274613
* AMDGPU: Fix return of non-void-returning shadersNicolai Haehnle2016-07-062-7/+6
| | | | | | | | | | | | | | | | | Summary: Since "AMDGPU: Fix verifier errors in SILowerControlFlow", the logic that ensures that a non-void-returning shader falls off the end of the last basic block was effectively disabled, since SI_RETURN is now used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96731 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21975 llvm-svn: 274612
* Vector GEP test: renamed + some commentsElena Demikhovsky2016-07-061-1/+8
| | | | | | Differential revision: http://reviews.llvm.org/D21957 llvm-svn: 274611
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