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* [WebAssembly] Assembler: support special floats: infinity / nanWouter van Oortmerssen2019-07-152-0/+29
| | | | | | | | | | | | | | | | | Summary: These are emitted as identifiers by the InstPrinter, so we should parse them as such. These could potentially clash with symbols of the same name, but that is out of our (the WebAssembly backend) control. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64770 llvm-svn: 366139
* [DirectoryWatcher][test] Relax test assumptionsJan Korous2019-07-151-44/+20
| | | | | | | | | Workaround for FSEvents sometimes sending notifications for events that happened before DirectoryWatcher was created. This caused tests to be flaky on green dragon. llvm-svn: 366138
* [DirectoryWatcher][NFC][test] Add typedef for enumJan Korous2019-07-151-22/+23
| | | | llvm-svn: 366137
* [ASan] Fix >80 character line.Matt Morehouse2019-07-151-1/+2
| | | | llvm-svn: 366136
* [AMDGPU] Enable merging m0 initializations.Austin Kerbow2019-07-152-22/+133
| | | | | | | | | | | | | | | | | | | | Summary: Enable hoisting and merging m0 defs that are initialized with the same immediate value. Fixes bug where removed instructions are not considered to interfere with other inits, and make sure to not hoist inits before block prologues. Reviewers: rampitec, arsenm Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64766 llvm-svn: 366135
* [ScopInfo][NFC] Add dot at the end of comment statement.Dominik Adamski2019-07-151-1/+1
| | | | llvm-svn: 366134
* [mips] Print BEQZL and BNEZL pseudo instructionsSimon Atanasyan2019-07-154-30/+30
| | | | | | One of the reasons - to be compatible with GNU tools. llvm-svn: 366133
* AMDGPU: Use standalone MUBUF load patternsMatt Arsenault2019-07-151-20/+37
| | | | | | | | | | | | | | | | | | We already do this for the flat and DS instructions, although it is certainly uglier and more verbose. This will allow using separate pattern definitions for extload and zextload. Currently we get away with using a single PatFrag with custom predicate code to check if the extension type is a zextload or anyextload. The generic mechanism the global isel emitter understands treats these as mutually exclusive. I was considering making the pattern emitter accept zextload or sextload extensions for anyextload patterns, but in global isel, the different extending loads have distinct opcodes, and there is currently no mechanism for an opcode matcher to try multiple (and there probably is very little need for one beyond this case). llvm-svn: 366132
* [TSan] Fix asm token errorJulian Lettner2019-07-151-1/+1
| | | | llvm-svn: 366131
* [LoopUnroll+LoopUnswitch] do not transform loops containing callbrNick Desaulniers2019-07-153-1/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is currently a correctness issue when unrolling loops containing callbr's where their indirect targets are being updated correctly to the newly created labels, but their operands are not. This manifests in unrolled loops where the second and subsequent copies of callbr instructions have blockaddresses of the label from the first instance of the unrolled loop, which would result in nonsensical runtime control flow. For now, conservatively do not unroll the loop. In the future, I think we can pursue unrolling such loops provided we transform the cloned callbr's operands correctly. Such a transform and its legalities are being discussed in: https://reviews.llvm.org/D64101 Link: https://bugs.llvm.org/show_bug.cgi?id=42489 Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI Reviewers: fhahn, hfinkel, efriedma Reviewed By: fhahn, hfinkel, efriedma Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D64368 llvm-svn: 366130
* TableGen/GlobalISel: Fix handling of truncstore patternsMatt Arsenault2019-07-152-1/+46
| | | | | | | | | | | | This was failing to import the AMDGPU truncstore patterns. The truncating stores from 32-bit to 8/16 were then somehow being incorrectly selected to a 4-byte store. A separate check is emitted for the LLT size in comparison to the specific memory VT, which looks strange to me but makes sense based on the hierarchy of PatFrags used for the default truncstore PatFrags. llvm-svn: 366129
* TableGen: Add address space to matchersMatt Arsenault2019-07-157-4/+253
| | | | | | | | | | | | | | | | | Currently AMDGPU uses a CodePatPred to check address spaces from the MachineMemOperand. Introduce a new first class property so that the existing patterns can be easily modified to uses the new generated predicate, which will also be handled for GlobalISel. I would prefer these to match against the pointer type of the instruction, but that would be difficult to get working with SelectionDAG compatbility. This is much easier for now and will avoid a painful tablegen rewrite for all the loads and stores. I'm also not sure if there's a better way to encode multiple address spaces in the table, rather than putting the number to expect. llvm-svn: 366128
* [clang] allow -fthinlto-index= without -x irBob Haarman2019-07-154-5/+19
| | | | | | | | | | | | | | | | | | | | Summary: Previously, passing -fthinlto-index= to clang required that bitcode files be explicitly marked by -x ir. This change makes us detect files with object file extensions as bitcode files when -fthinlto-index= is present, so that explicitly marking them is no longer necessary. Explicitly specifying -x ir is still accepted and continues to be part of the test case to ensure we continue to support it. Reviewers: tejohnson, rnk, pcc Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64610 llvm-svn: 366127
* [TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.9Julian Lettner2019-07-151-22/+5
| | | | | | | Switch over to computing the xor key in C, instead of assembly for Linux/AArch64. llvm-svn: 366126
* AMDGPU/GlobalISel: Allow scalar s1 and/or/xorMatt Arsenault2019-07-156-168/+1964
| | | | | | | | If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to whether the result is 0. If the inputs are SCC, these can be copied to a 32-bit SGPR to produce an SCC result. llvm-svn: 366125
* [libc++] Implement P0433: deduction guides for <unordered_map>Louis Dionne2019-07-158-7/+1106
| | | | | | | | Thanks to Arthur O'Dwyer for the patch. Differential Revision: https://reviews.llvm.org/D58590 llvm-svn: 366124
* ARM MTE stack sanitizer.Evgeniy Stepanov2019-07-1528-21/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | Add "memtag" sanitizer that detects and mitigates stack memory issues using armv8.5 Memory Tagging Extension. It is similar in principle to HWASan, which is a software implementation of the same idea, but there are enough differencies to warrant a new sanitizer type IMHO. It is also expected to have very different performance properties. The new sanitizer does not have a runtime library (it may grow one later, along with a "debugging" mode). Similar to SafeStack and StackProtector, the instrumentation pass (in a follow up change) will be inserted in all cases, but will only affect functions marked with the new sanitize_memtag attribute. Reviewers: pcc, hctim, vitalybuka, ostannard Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D64169 llvm-svn: 366123
* Constrain workaround to avoid affecting other buildbotsEric Fiselier2019-07-151-2/+4
| | | | llvm-svn: 366122
* AMDGPU/GlobalISel: Select G_AND/G_OR/G_XORMatt Arsenault2019-07-155-24/+1828
| | | | llvm-svn: 366121
* AMDGPU/GlobalISel: Don't constrain source register of VCC copiesMatt Arsenault2019-07-152-4/+47
| | | | | | | | | | | | | This is a hack until I come up with a better way of dealing with the pseudo-register banks used for boolean values. If the use instruction constrains the register, the selector for the def instruction won't see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have been SCCRegBank or VCCRegBank in wave32. This is necessary to successfully select branches with and and/or/xor condition. llvm-svn: 366120
* AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copiesMatt Arsenault2019-07-152-13/+43
| | | | | | | | | The extra test change is correct, although how it arrives there is a bug that needs work. With wave32, the test for isVCC ambiguously reports true for an SCC or VCC source. A new allocatable pseudo register class for SCC may be necesssary. llvm-svn: 366119
* AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCCMatt Arsenault2019-07-152-0/+30
| | | | llvm-svn: 366118
* AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCCMatt Arsenault2019-07-152-26/+59
| | | | | | This was emitting a copy from a 32-bit register to a 64-bit. llvm-svn: 366117
* AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELTMatt Arsenault2019-07-153-4/+71
| | | | llvm-svn: 366116
* AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELTMatt Arsenault2019-07-153-103/+135
| | | | | | Turn the constant cases into G_EXTRACTs. llvm-svn: 366115
* AMDGPU/GlobalISel: Fix G_ICMP for wave32Matt Arsenault2019-07-152-8/+9
| | | | llvm-svn: 366114
* GlobalISel: Implement narrowScalar for vector extract/insert indexesMatt Arsenault2019-07-153-2/+74
| | | | llvm-svn: 366113
* AMDGPU: Fix missing immarg from interp intrinsicsMatt Arsenault2019-07-152-5/+101
| | | | llvm-svn: 366110
* [FileCheck] Store line numbers as optional valuesThomas Preud'homme2019-07-153-38/+44
| | | | | | | | | | | | | | | | | | | | Summary: Processing of command-line definition of variable and logic around implicit not directives both reuse parsing code that expects a line number to be defined. So far, a special line number of 0 was used for those users of the parsing code where a line number does not make sense. This commit instead represents line numbers as Optional values so that they can be None for those cases. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D64639 llvm-svn: 366109
* [cmake] Don't set install rules for tblgen if building utils is disabledKeno Fischer2019-07-151-1/+1
| | | | | | | | | | | | | | | | | Summary: This is a follow up to D64032. Afterwards if building utils is disabled and cross compilation is attempted, CMake will complain that adding `install()` directives to targets with EXCLUDE_FROM_ALL set is "undefined". Indeed, it appears depending on the CMake version and the selected Generator, the install rule will error because the underlying target isn't built. Fix that by not adding the install rule if building utils is not requested. Note that this doesn't prevent building tblgen as a dependency in not cross-build, even if building tools is disabled. Reviewed By: smeenai Differential Revision: https://reviews.llvm.org/D64225 llvm-svn: 366108
* Expand comment about how StringsToBuckets was computed, and add more entriesNico Weber2019-07-151-1/+14
| | | | | | | | | | | | | | | | | The construction was explained in https://reviews.llvm.org/D44810?id=139526#inline-391999 but reading the code shouldn't require hunting down old reviews to understand it. The precomputed list was missing an entry for the empty list case, and one entry at the very end. (The current last entry is the last one where 3 * BucketCount fits in a signed int, but the reference implementation uses unsigneds as far as I can tell, so there's room for one more entry.) No behavior change for inputs seen in practice. Differential Revision: https://reviews.llvm.org/D64738 llvm-svn: 366107
* [ARM] MVE vector for 64bit typesDavid Green2019-07-1519-40/+1875
| | | | | | | | | | | | We need to make sure that we are sensibly dealing with vectors of types v2i64 and v2f64, even if most of the time we cannot generate native operations for them. This mostly adds a lot of testing, plus fixes up a couple of the issues found. And, or and xor can be legal for v2i64, and shifts combining needs a slight fixup. Differential Revision: https://reviews.llvm.org/D64316 llvm-svn: 366106
* [sanitizers][windows][mingw32] Mingw32 RTL fixesMatthew G McGovern2019-07-151-44/+44
| | | | | | | | | RTL interception broke mingw32, this should fix those builds by removing dependency on windows.h reviewed in https://reviews.llvm.org/D64694 llvm-svn: 366105
* [WebAssembly] Assembler: recognize .init_array as data section.Wouter van Oortmerssen2019-07-152-3/+15
| | | | | | | | | | | | Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64602 llvm-svn: 366104
* AMDGPU/GlobalISel: Widen vector extractsMatt Arsenault2019-07-152-5/+374
| | | | llvm-svn: 366103
* AMDGPU/GlobalISel: Handle llvm.amdgcn.if.breakMatt Arsenault2019-07-154-0/+85
| | | | llvm-svn: 366102
* AMDGPU: Remove reserved value accidentally left in for gfx908Konstantin Zhuravlyov2019-07-151-2/+1
| | | | llvm-svn: 366101
* AMDGPU/GlobalISel: Select llvm.amdgcn.end.cfMatt Arsenault2019-07-154-0/+94
| | | | llvm-svn: 366099
* [x86] try to keep FP casted+truncated+extracted vector element out of GPRsSanjay Patel2019-07-153-19/+54
| | | | | | | | | | | | | | | | | | inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0) We have pseudo-vectorization of scalar int to FP casts, so this tries to make that more likely by replacing a truncate with a bitcast. I didn't see any test diffs starting from 'uitofp', so I left that as a TODO. We can't only match the shorter trunc+extract pattern because there's an opposing transform somewhere, so we infinite loop. Waiting to try this during lowering is another possibility. A motivating case is shown in PR39975 and included in the test diffs here: https://bugs.llvm.org/show_bug.cgi?id=39975 Differential Revision: https://reviews.llvm.org/D64710 llvm-svn: 366098
* [llvm-lib] Add a dependency to intrinsics_gen to the LLVMLibDriver buildStella Stamenova2019-07-151-0/+3
| | | | | | | | | | | | | | | | | | Summary: Occasionally the build of LLVMLibDriver will fail because Attributes.inc has not been generated yet. Add an explicit dependency, so that we can guarantee that the file has been generated before LLVMLibDriver is build. ##[error]llvm\include\llvm\IR\Attributes.h(73,0): Error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory llvm\include\llvm/IR/Attributes.h(73): fatal error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory [LLVMLibDriver.vcxproj] Reviewers: asmith Subscribers: mgorny, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64357 llvm-svn: 366097
* [X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is ↵Craig Topper2019-07-151-2/+5
| | | | | | | | | | | | | | | | | | | | out of range. I think we only turn out of range shiftss to undef when all elements are out of range or the shift amount is a splat out of range. I'm not sure which, I didn't check. During lowering we can split a shift where some elements are out of range into multiple shifts. This can create a new shift with a splat shift amount that is out of range. This patch returns undef for this case. Fixes PR42615. Differential Revision: https://reviews.llvm.org/D64699 llvm-svn: 366096
* Reland "[COFF] Add null check in case of symbols defined in LTO blobs"Reid Kleckner2019-07-154-1/+141
| | | | | | | | | | This reverts r365990 (git commit 1a6053ebc61cb0b8146f5ca27b74859a9a91e0a3) The test no longer depends on the Visual C++ libraries. I confirmed that the crash still reproduces with the new test case if I remove the null check. llvm-svn: 366095
* AMDGPU: Add 24-bit mul intrinsicsMatt Arsenault2019-07-159-11/+751
| | | | | | | | | | | Insert these during codegenprepare. This works around a DAG issue where generic combines eliminate the and asserting the high bits are zero, which then exposes an unknown read source to the mul combine. It doesn't worth the hassle of trying to insert an AssertZext or something to try to deal with it. llvm-svn: 366094
* Add some release notes for 9.0 releaseMatt Arsenault2019-07-151-1/+11
| | | | llvm-svn: 366093
* [AMDGPU] Copy missing predicate from pseudo to realStanislav Mekhanoshin2019-07-151-0/+1
| | | | | | | | NFC at the momemnt, needed for future commit. Differential Revision: https://reviews.llvm.org/D64761 llvm-svn: 366092
* Update __VERSION__ to remove the hardcoded 4.2.1 versionSylvestre Ledru2019-07-154-6/+13
| | | | | | | | | | | | | | | | | | Summary: Just like in https://reviews.llvm.org/D56803 for -dumpversion Reviewers: rnk Reviewed By: rnk Subscribers: dexonsmith, lebedev.ri, hubert.reinterpretcast, xbolva00, fedor.sergeev, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63048 llvm-svn: 366091
* [FunctionAttrs] Remove readonly and writeonly assertionJohannes Doerfert2019-07-152-2/+25
| | | | | | | | | | | | | There are scenarios where mutually recursive functions may cause the SCC to contain both read only and write only functions. This removes an assertion when adding read attributes which caused a crash with a the provided test case, and instead just doesn't add the attributes. Patch by Luke Lau <luke.lau@intel.com> Differential Revision: https://reviews.llvm.org/D60761 llvm-svn: 366090
* [ARM] Minor formatting in ARMInstrMVE.td. NFCDavid Green2019-07-151-34/+34
| | | | llvm-svn: 366089
* Use a unique_ptr instead of manual memory management for LineTableNico Weber2019-07-152-4/+2
| | | | llvm-svn: 366088
* AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTORMatt Arsenault2019-07-152-0/+156
| | | | llvm-svn: 366087
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