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* Try number 2 for fixing bot failuresTeresa Johnson2020-01-135-22/+32
| | | | | | | | Additional fixes for bot failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f. Remove more exact matching on AnalyisManagers, as they can vary. Also allow different orders between LoopAnalysis and BranchProbabilityAnalysis as that can vary due to both being accessed in the parameter list of a call.
* AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}Matt Arsenault2020-01-135-0/+99
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* [SelectionDAG] ComputeNumSignBits add getValidMaximumShiftAmountConstant() ↵Simon Pilgrim2020-01-132-24/+40
| | | | | | for ISD::SHL support Allows us to handle non-uniform SHL shifts to determine the minimum number of sign bits remaining (based off the maximum shift amount value)
* AMDGPU/GlobalISel: Set insert point after waterfall loopMatt Arsenault2020-01-131-2/+3
| | | | | | | | | The current users of the waterfall loop utility functions do not make use of the restored original insert point. The insertion is either done, or they set the insert point somewhere else. A future change will want to insert instructions after the waterfall loop, but figuring out the point after the loop is more difficult than ensuring the insert point is there after the loop.
* AMDGPU/GlobalISel: Add some baseline tests for vector extractMatt Arsenault2020-01-131-0/+468
| | | | | A future change will try to fold constant offsets into the loop which these will stress.
* AMDGPU/GlobalISel: Fix branch targets when emitting SI_IFMatt Arsenault2020-01-132-7/+91
| | | | | | | | The branch target needs to be changed depending on whether there is an unconditional branch or not. Loops also need to be similarly fixed, but compiling a simple testcase end to end requires another set of patches that aren't upstream yet.
* AMDGPU/GlobalISel: Simplify assertMatt Arsenault2020-01-131-11/+3
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* [X86][SSE] Add sitofp(shl(sext(x),y)) test case with non-uniform shift valueSimon Pilgrim2020-01-131-0/+49
| | | | Shows that for non-uniform SHL shifts we fail to determine the minimum number of sign bits remaining (based off the maximum shift amount value)
* [lldb/Docs] Extend description section of the main pageJonas Devlieghere2020-01-131-2/+9
| | | | | The current description is a bit terse. I've copy/pasted the introduction form the website.
* Fix tests for builtbot failuresTeresa Johnson2020-01-135-24/+24
| | | | | | | | | Should fix most of the buildbot failures from 2af97be8027a0823b88d4b6a07fc5eedb440bc1f, by loosening up the matching on the AnalysisProxy output. Added in --dump-input=fail on the one test that appears to be something different, so I can hopefully debug it better.
* [lldb/Scripts] Remove SWIG botJonas Devlieghere2020-01-135-621/+0
| | | | | | This is no longer used or maintained. Differential revision: https://reviews.llvm.org/D72539
* [LegalizeTypes] Add SoftenFloatResult support for ↵Andrew Wei2020-01-142-8/+34
| | | | | | | | | STRICT_SINT_TO_FP/STRICT_UINT_TO_FP Some target like arm/riscv with soft-float will have compiling crash when using -fno-unsafe-math-optimization option. This patch will add the missing strict FP support to SoftenFloatRes_XINT_TO_FP. Differential Revision: https://reviews.llvm.org/D72277
* [SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ↵Simon Pilgrim2020-01-132-55/+18
| | | | | | ISD::SRA support Allows us to handle more non-uniform SRA sign bits cases
* [X86][SSE] Add sitofp(ashr(x,y)) test case with non-uniform shift valueSimon Pilgrim2020-01-131-0/+94
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* [X86] Add AVX2 known signbits codegen testsSimon Pilgrim2020-01-131-67/+128
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* [Scheduler] Remove superfluous casts. NFCDavid Green2020-01-132-5/+3
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* [AArch64][SVE] Add patterns for some arith SVE instructions.Danilo Carvalho Grael2020-01-136-10/+432
| | | | | | | | | | | Summary: Add patterns for the following instructions: - smax, smin, umax, umin Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin Subscribers: amehsan Differential Revision: https://reviews.llvm.org/D71779
* [ThinLTO] Add additional ThinLTO pipeline testing with new PMTeresa Johnson2020-01-138-0/+1244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I've added some more extensive ThinLTO pipeline testing with the new PM, motivated by the bug fixed in D72386. I beefed up llvm/test/Other/new-pm-pgo.ll a little so that it tests ThinLTO pre and post link with PGO, similar to the testing for the default pipelines with PGO. Added new pre and post link PGO tests for both instrumentation and sample PGO that exhaustively test the pipelines at different optimization levels via opt. Added a clang test to exhaustively test the post link pipeline invoked for distributed builds. I am currently only testing O2 and O3 since these are the most important for performance. It would be nice to add similar exhaustive testing for full LTO, and for the old PM, but I don't have the bandwidth now and this is a start to cover some of the situations that are not currently default and were under tested. Reviewers: wmi Subscribers: mehdi_amini, inglorion, hiraditya, steven_wu, dexonsmith, jfb, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72538
* [DebugInfo] Make debug line address size mismatch non-fatal to parsingJames Henderson2020-01-132-19/+72
| | | | | | | | | Reasonable assumptions can be made when a parsed address length does not match the expected length, so there's no need for this to be fatal. Reviewed by: ikudrin Differential Revision: https://reviews.llvm.org/D72154
* [mlir] m_Constant()Lorenzo Chelini2020-01-134-3/+16
| | | | | | Summary: Introduce m_Constant() which allows matching a constant operation without forcing the user also to capture the attribute value. Differential Revision: https://reviews.llvm.org/D72397
* [mlir] Added missing GPU lowering ops.Julian Gross2020-01-134-2/+106
| | | | | | | | | | | Summary: This diff adds missing GPU lowering ops to MLIR. Reviewers: herhut, pifon2a, ftynse Tags: #pre-merge_beta_testing, #llvm Differential Revision: https://reviews.llvm.org/D72439
* [Inlining] Add PreInlineThreshold for the new pass managerKazu Hirata2020-01-131-2/+6
| | | | | | | | | | | | | | | Summary: This patch makes it easy to try out different preinlining thresholds with a command-line switch just like -preinline-threshold for the legacy pass manager. Reviewers: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72618
* [mlir][Linalg] Update ReshapeOp::build to be more idiomaticNicolas Vasilache2020-01-134-9/+82
| | | | | | | | | | | | | | Summary: This diff makes it easier to create a `linalg.reshape` op and adds an EDSC builder api test to exercise the new builders. Reviewers: ftynse, jpienaar Subscribers: mehdi_amini, rriddle, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72580
* [Clang][Driver] Re-use the calling process instead of creating a new process ↵Alexandre Ganea2020-01-1313-44/+157
| | | | | | | | | | | | | | | for the cc1 invocation With this patch, the clang tool will now call the -cc1 invocation directly inside the same process. Previously, the -cc1 invocation was creating, and waiting for, a new process. This patch therefore reduces the number of created processes during a build, thus it reduces build times on platforms where process creation can be costly (Windows) and/or impacted by a antivirus. It also makes debugging a bit easier, as there's no need to attach to the secondary -cc1 process anymore, breakpoints will be hit inside the same process. Crashes or signaling inside the -cc1 invocation will have the same side-effect as before, and will be reported through the same means. This behavior can be controlled at compile-time through the CLANG_SPAWN_CC1 cmake flag, which defaults to OFF. Setting it to ON will revert to the previous behavior, where any -cc1 invocation will create/fork a secondary process. At run-time, it is also possible to tweak the CLANG_SPAWN_CC1 environment variable. Setting it and will override the compile-time setting. A value of 0 calls -cc1 inside the calling process; a value of 1 will create a secondary process, as before. Differential Revision: https://reviews.llvm.org/D69825
* [RISCV] Handle globals and block addresses in asm operandsLuís Marques2020-01-132-2/+52
| | | | | | | | | | Summary: These seem to be the machine operand types currently needed by the RISC-V target. Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D72275
* Fix cppcheck uninitialized variable in DiffTree() constructor warning. NFCI.Simon Pilgrim2020-01-131-2/+1
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* Merge isVectorType() and getAs<VectorType> calls to silence clang static ↵Simon Pilgrim2020-01-131-2/+1
| | | | analyzer warning. NFCI.
* Fix some cppcheck shadow variable warnings. NFCI.Simon Pilgrim2020-01-131-15/+13
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* Fix "pointer is null" static analyzer warnings. NFCI.Simon Pilgrim2020-01-131-2/+2
| | | | Use castAs<> instead of getAs<> since the pointers are always dereferenced and castAs will perform the null assertion for us.
* Sema::getOwningModule - take const Decl* type.Simon Pilgrim2020-01-132-5/+6
| | | | Fixes static analyzer warning that const_cast was being used despite only const methods being called.
* Add missing triples to tests in 0c29d3ff2233696f663ae34a8aeda23c750ac68f so ↵Sam McCall2020-01-132-2/+2
| | | | they target the right arch.
* [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or belowPablo Barrio2020-01-1313-130/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some instructions are implemented in the HINT space to allow compiling code common to CPUs regardless of whether they feature PAC or not, and still benefit from PAC protection in the PAC-enabled CPUs. The 8.3-specific mnemonics were currently enabled in any architecture, and LLVM was emitting them in assembly files when PAC code generation was enabled. This was ok for compilations where both LLVM codegen and the integrated assembler were used. However, the LLVM codegen was not compatible with other assemblers (e.g. GAS). Given the fact that the approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes LLVM to emit HINT when building for Armv8.2-A and below, instead of PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible with other assemblers. Reviewers: samparker, chill, LukeCheeseman Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71658
* [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbolsAlex Richardson2020-01-132-53/+99
| | | | | | | | | | | | | | The R_(MICRO)MIPS_JALR optimization only works when used against functions. Using the relocation against a data symbol (e.g. function pointer) will cause some linkers that don't ignore the hint in this case (e.g. LLD prior to commit 5bab291b7b) to generate a relative branch to the data symbol which crashes at run time. Before this patch, LLVM was erroneously emitting these relocations against local-dynamic TLS function pointers and global function pointers with internal visibility. Reviewers: atanasyan, jrtc27, vstefanovic Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72571
* [MIPS][ELF] Use PC-relative relocations in .eh_frame when possibleAlex Richardson2020-01-135-41/+148
| | | | | | | | | | | | | | | | | | | | When compiling position-independent executables, we now use DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the large code model case. When using the large code model, we fall back to the previous behaviour of generating absolute relocations. With this change clang-generated .o files can be linked by LLD without having to pass -Wl,-z,notext (which creates text relocations). This is simpler than the approach used by ld.bfd, which rewrites the .eh_frame section to convert absolute relocations into relative references. I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations for MIPS ouput at some point. However, I also checked that recent ld.bfd can process the clang-generated .o files so this no longer seems true. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72228
* [InstSimplify] move tests for select from InstCombine; NFCSanjay Patel2020-01-132-33/+24
| | | | | | InstCombine has transforms that would enable these simplifications in an indirect way, but those transforms are unsafe and likely to be removed.
* [SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for ↵Simon Pilgrim2020-01-131-15/+8
| | | | | | shift opcodes getValidShiftAmountConstant handles out of bounds shift amounts for us, allowing us to remove the local handling.
* [SelectionDAG] ComputeKnownBits - Add DemandedElts support to ↵Simon Pilgrim2020-01-133-17/+17
| | | | getValidShiftAmountConstant/getValidMinimumShiftAmountConstant()
* [X86] Add knownbits tests showing missing shift amount demanded elts handling.Simon Pilgrim2020-01-132-0/+62
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* Revert "[libc++] Explicitly enumerate std::string external instantiations."Oliver Stannard2020-01-134-62/+4
| | | | | | | This is causing failures for multiple buildbots and bootstrap builds, details at https://reviews.llvm.org/rG61bd1920. This reverts commit 61bd19206f61ace4b007838a2ff8884a13ec0374.
* [FPEnv] Fix chain handling for fpexcept.strict nodesUlrich Weigand2020-01-1310-471/+542
| | | | | | | | | | | | | | | | | We need to ensure that fpexcept.strict nodes are not optimized away even if the result is unused. To do that, we need to chain them into the block's terminator nodes, like already done for PendingExcepts. This patch adds two new lists of pending chains, PendingConstrainedFP and PendingConstrainedFPStrict to hold constrained FP intrinsic nodes without and with fpexcept.strict markers. This allows not only to solve the above problem, but also to relax chains a bit further by no longer flushing all FP nodes before a store or other memory access. (They are still flushed before nodes with other side effects.) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D72341
* GlobalISel: Fix assertion on wide G_ZEXT sourcesMatt Arsenault2020-01-132-1/+27
| | | | It's possible to have a type that needs a mask greater than 64-bits.
* [llvm-exegesis] Remove unneeded std::move()Miloš Stojanović2020-01-131-1/+1
| | | | | | | | | | | Caught by buildbot breakage: /home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move] return std::move(Instructions); ^ /home/docker/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp:89:12: note: remove std::move call here return std::move(Instructions); ^~~~~~~~~~ ~
* [lldb][NFC] Remove debug print statement from TestExprDiagnostics.pyRaphael Isemann2020-01-131-1/+0
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* [clang] Remove raw string literals in macrosOliver Stannard2020-01-132-86/+96
| | | | | Older (but still supported) versions of GCC don't handle C++11 raw string literals in macro parameters correctly.
* [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ↵Simon Pilgrim2020-01-132-3/+5
| | | | | | ISD::SHL support As mentioned on D72573
* [X86][SSE] Add knownbits test showing missing ↵Simon Pilgrim2020-01-131-0/+33
| | | | | | getValidMinimumShiftAmountConstant() ISD::SHL support As mentioned on D72573
* [clangd] Remove raw string literals in macrosOliver Stannard2020-01-131-12/+16
| | | | | Older (but still supported) versions of GCC don't handle C++11 raw string literals in macro parameters correctly.
* [llvm-exegesis][mips] Expand loadImmediate()Miloš Stojanović2020-01-133-18/+133
| | | | | | | Add support for loading 32-bit immediates and enable the use of GPR64 registers. Differential Revision: https://reviews.llvm.org/D71873
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in ↵Simon Pilgrim2020-01-1320-260/+153
| | | | | | | | | | LSHR/SHL (PR44526) As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value. This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits. Differential Revision: https://reviews.llvm.org/D72573
* [X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI.Simon Pilgrim2020-01-131-2/+2
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