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* Fix typoXinliang David Li2016-05-212-2/+2
| | | | llvm-svn: 270338
* [profile] Static counter allocation for value profiling (part-2)Xinliang David Li2016-05-2111-24/+136
| | | | | | Differential Revision: http://reviews.llvm.org/D20460 llvm-svn: 270337
* [profile] Static counter allocation for value profiling (part-1)Xinliang David Li2016-05-215-13/+161
| | | | | | Differential Revision: http://reviews.llvm.org/D20459 llvm-svn: 270336
* [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 ↵Craig Topper2016-05-211-8/+8
| | | | | | for integer types when only AVX1 is supported. llvm-svn: 270335
* [AVX512] Add patterns for extracting subvectors and storing to memory.Craig Topper2016-05-214-16/+99
| | | | llvm-svn: 270334
* [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily ↵Craig Topper2016-05-211-2/+2
| | | | | | used to indicating the zero masking behavior which is not the case here. NFC llvm-svn: 270333
* [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to ↵Craig Topper2016-05-211-2/+2
| | | | | | reflect the fact that memory is the destination. llvm-svn: 270332
* [AVX512] Fix copy/paste mistake a I made in a comment.Craig Topper2016-05-211-1/+1
| | | | llvm-svn: 270331
* [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16Simon Pilgrim2016-05-212-9/+7
| | | | | | | | | | Ensure _mm256_extract_epi8 and _mm256_extract_epi16 zero extend their i8/i16 result to i32. This matches _mm_extract_epi8 and _mm_extract_epi16. Fix for PR27594 Differential Revision: http://reviews.llvm.org/D20468 llvm-svn: 270330
* Fix 80-column violation.Chad Rosier2016-05-211-1/+2
| | | | llvm-svn: 270329
* [ELF] Take into account offset in the output section when read addends for a ↵Simon Atanasyan2016-05-213-3/+26
| | | | | | non-alloc input section llvm-svn: 270328
* Use uintX_t instead of unsigned.Rui Ueyama2016-05-212-2/+2
| | | | | | | | This fixes a potential bug when cross linking very large executables on LLP64 machines such as Windows. On such platform, uintX_t is 64 bits while unsigned is 32 bits. llvm-svn: 270327
* Remove dead variable.Rui Ueyama2016-05-211-2/+1
| | | | llvm-svn: 270326
* Split EHOutputSection<ELFT>::addSectionAux. NFC.Rui Ueyama2016-05-211-12/+20
| | | | llvm-svn: 270325
* Swap the arguments of writeAlignedCieOrFde. NFC.Rui Ueyama2016-05-211-7/+7
| | | | | | | | Most functions take destination buffers as the first arguments just like memcpy, so this order is easier to read. Also simplified the function. llvm-svn: 270324
* [LiveIntervalAnalysis] Don't dereference an end iterator in ↵Hal Finkel2016-05-211-1/+1
| | | | | | | | | | | | | | | | repairIntervalsInRange This fixes a bug introduced in: r262115 - CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC The iterator End here might == MBB->end(), and so we can't unconditionally dereference it. This often goes unnoticed (I don't have a test case that always crashes, and ASAN does not catch it either) because the function call arguments are turned right back into iterators. MachineInstrBundleIterator's constructor, however, does have an assert which might randomly fire. llvm-svn: 270323
* [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.Michael Zuckerman2016-05-216-27/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D20438 llvm-svn: 270322
* [Clang][AVX512][intrinsics] Fix vscalef intrinsics.Michael Zuckerman2016-05-218-43/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D20324 llvm-svn: 270321
* [llvm-readobj] - Teach readobj to recognize SHF_COMPRESSED flag.George Rimar2016-05-213-2/+19
| | | | | | | | | | | | | | | | | | | | | | | Main problem here was that SHF_COMPRESSED has the same value with XCORE_SHF_CP_SECTION, which was included as standart (common) flag. As far I understand xCore is a family of controllers and it that means it's constant should be processed separately, only if e_machine == EM_XCORE, otherwise llvm-readobj would output different constants twice for compressed section: Flags [ .. SHF_COMPRESSED (0x800) .. XCORE_SHF_CP_SECTION (0x800) .. ] what probably does not make sence if you're not working with xcore file. Differential revision: http://reviews.llvm.org/D20273 llvm-svn: 270320
* [tsan] Don't abort when a deadlock detector finds a mutex cycle longer than 10Kuba Brecka2016-05-213-3/+50
| | | | | | | | In one of the already existing apps that I'm testing TSan on, I really see a mutex path that is longer than 10 (but not by much, something like 11-13 actually). Let's raise this to 20 and weaken the assertion so we don't crash. Differential Revision: http://reviews.llvm.org/D20427 llvm-svn: 270319
* [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable ↵Craig Topper2016-05-216-20/+34
| | | | | | AVX2 versions of vector extract when AVX512VL is enabled. llvm-svn: 270318
* [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when ↵Craig Topper2016-05-213-34/+42
| | | | | | AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones. llvm-svn: 270317
* [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL ↵Craig Topper2016-05-212-7/+7
| | | | | | is enabled. llvm-svn: 270316
* [AVX512] Use update_llc_test_checks to update some tests so we can see all ↵Craig Topper2016-05-213-4415/+7909
| | | | | | the instruction encodings and ensure everything is with EVEX. llvm-svn: 270315
* [SimplifyCFG] Remove cleanuppads which are empty except for calls to ↵David Majnemer2016-05-212-5/+48
| | | | | | | | | | | | | lifetime.end A cleanuppad is not cheap, they turn into many instructions and result in additional spills and fills. It is not worth keeping a cleanuppad around if all it does is hold a lifetime.end instruction. N.B. We first try to merge the cleanuppad with another cleanuppad to avoid dropping the lifetime and debug info markers. llvm-svn: 270314
* [AVX512] Fix test cases I missed in r270311.Craig Topper2016-05-211-4/+4
| | | | llvm-svn: 270313
* AMDGPU: Define priorities for register classesMatt Arsenault2016-05-2110-51/+74
| | | | | | | | | | Allocating larger register classes first should give better allocation results (and more importantly for myself, make the lit tests more stable with respect to scheduler changes). Patch by Matthias Braun llvm-svn: 270312
* [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the ↵Craig Topper2016-05-211-4/+4
| | | | | | AVX512VL/AVX512BWI equivalents are available. llvm-svn: 270311
* [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering ↵Craig Topper2016-05-212-12/+24
| | | | | | instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers. llvm-svn: 270310
* [IRCE] Don't use an allocator for range checks; NFCSanjoy Das2016-05-211-37/+28
| | | | | | | | The InductiveRangeCheck struct is only five words long; so passing these around value is fine. The allocator makes the code look more complex than it is. llvm-svn: 270309
* [IRCE] Don't pass IRBuilder<> where unnecessary; NFCSanjoy Das2016-05-211-8/+6
| | | | llvm-svn: 270308
* AMDGPU: Cleanup lowering actionsMatt Arsenault2016-05-215-324/+379
| | | | | | | | These are kind of a mess and hard to follow, particularly for loads and stores. Fix various redundant, unnecessary and dead settings. llvm-svn: 270307
* [GuardWidening] Fix incorrect use of remove_ifSanjoy Das2016-05-212-25/+67
| | | | | | | | | | | I had used `std::remove_if` under the assumption that it moves the predicate matching elements to the end, but actaully the elements remaining towards the end (after the iterator returned by `std::remove_if`) are indeterminate. Fix the bug (and make the code more straightforward) by using a temporary SmallVector, and add a test case demonstrating the issue. llvm-svn: 270306
* AMDGPU: Fix high bits after division optimizationMatt Arsenault2016-05-217-58/+365
| | | | | | | This is essentially doing a 24-bit signed division with FP. We need to truncate to the N bit result. llvm-svn: 270305
* [RegBankSelect] Compute the repairing cost for copies.Quentin Colombet2016-05-212-15/+49
| | | | | | | Prior to this patch, we were using 1 for all the repairing costs. Now, we use the information from the target to get this information. llvm-svn: 270304
* [RegisterBankInfo] Fix the initialization of the map VT to RegBank.Quentin Colombet2016-05-211-1/+4
| | | | | | Prior to this patch we could have read uninitialized memory. llvm-svn: 270303
* [AVR] Add AVRMCAsmInfoDylan McKay2016-05-213-0/+60
| | | | llvm-svn: 270302
* AMDGPU: Fix verifier error when spilling SGPRsMatt Arsenault2016-05-212-2/+15
| | | | | | | | | | | The current SGPR spilling test does not stress this because it is using s_buffer_load instructions to increase SGPR pressure and spill, but their output operands have the same SReg_32_XM0 constraint. This fixes an error when the SReg_32 output from most instructions is spilled. llvm-svn: 270301
* AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0Matt Arsenault2016-05-211-6/+5
| | | | llvm-svn: 270300
* Fix implicit type conversion. NFC.Chris Bieneman2016-05-211-1/+1
| | | | llvm-svn: 270299
* [AVR] Fix header files in MCTargetDescDylan McKay2016-05-216-4/+39
| | | | | | | Everything now compiles successfully, but there are still undefined references. llvm-svn: 270298
* AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault2016-05-215-9/+33
| | | | llvm-svn: 270297
* AMDGPU: Implement ReverseBranchConditionMatt Arsenault2016-05-213-6/+12
| | | | llvm-svn: 270296
* AMDGPU: Implement AnalyzeBranchMatt Arsenault2016-05-2111-42/+214
| | | | | | Original patch by Tom Stellard llvm-svn: 270295
* [WebAssembly] Optimize away return instructions using fallthroughs.Dan Gohman2016-05-2147-59/+201
| | | | | | | | | This saves a small amount of code size, and is a first small step toward passing values on the stack across block boundaries. Differential Review: http://reviews.llvm.org/D20450 llvm-svn: 270294
* Fix constant folding of addrspacecast of nullMatt Arsenault2016-05-214-4/+73
| | | | | | | This should not be making assumptions on the value of the casted pointer. llvm-svn: 270293
* [AVR] Fix signuature of AVRTargetMachine constructorDylan McKay2016-05-202-4/+7
| | | | llvm-svn: 270292
* LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun2016-05-207-250/+77
| | | | | | | | | | | | | | | | | | | | | We now use LiveRangeCalc::extendToUses() instead of a specially designed algorithm in constructMainRangeFromSubranges(): - The original motivation for constructMainRangeFromSubranges() were differences between the main liverange and subranges because of hidden dead definitions. This case however cannot happen anymore with the DetectDeadLaneMasks pass in place. - It simplifies the code. - This fixes a longstanding bug where we did not properly create new SSA values on merging control flow (the MachineVerifier missed most of these cases). - Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and LiveRangeCalc to better match the implementation/available helper functions. This re-applies r269016. The fixes from r270290 and r270259 should avoid the machine verifier problems this time. llvm-svn: 270291
* MachineVerifier: subregs so not require defs/valnos on every pathMatthias Braun2016-05-202-2/+29
| | | | | | | | | | | It is fine for subregister ranges to be undefined on some CFG paths as we may have a "vregX:other_subreg<read-undef> =" def on that path. We do not (and should not) have live segments for the subregister ranges. The MachineVerifier should not complain about this. This is a slight variant of http://llvm.org/PR27705 llvm-svn: 270290
* Fix struct member names and simplify. NFC.Rui Ueyama2016-05-201-6/+4
| | | | llvm-svn: 270289
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