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* [Preprocessor] Fix incorrect token caching that occurs when lexing _PragmaAlex Lorenz2017-02-244-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in macro argument pre-expansion mode when skipping a function body This commit fixes a token caching problem that currently occurs when clang is skipping a function body (e.g. when looking for a code completion token) and at the same time caching the tokens for _Pragma when lexing it in macro argument pre-expansion mode. When _Pragma is being lexed in macro argument pre-expansion mode, it caches the tokens so that it can avoid interpreting the pragma immediately (as the macro argument may not be used in the macro body), and then either backtracks over or commits these tokens. The problem is that, when we're backtracking/committing in such a scenario, there's already a previous backtracking position stored in BacktrackPositions (as we're skipping the function body), and this leads to a situation where the cached tokens from the pragma (like '(' 'string_literal' and ')') will remain in the cached tokens array incorrectly even after they're consumed (in the case of backtracking) or just ignored (in the case when they're committed). Furthermore, what makes it even worse, is that because of a previous backtracking position, the logic that deals with when should we call ExitCachingLexMode in CachingLex no longer works for us in this situation, and more tokens in the macro argument get cached, to the point where the EOF token that corresponds to the macro argument EOF is cached. This problem leads to all sorts of issues in code completion mode, where incorrect errors get presented and code completion completely fails to produce completion results. rdar://28523863 Differential Revision: https://reviews.llvm.org/D28772 llvm-svn: 296140
* Fixed IntOperandMatcher::emitCxxPredicateExpr argumentsSimon Pilgrim2017-02-241-1/+1
| | | | | | Extra const in the StringRef argument meant that MSVC complained about it not correctly overriding from OperandPredicateMatcher::emitCxxPredicateExpr (which didn't have the const) llvm-svn: 296138
* [DAGCombiner] add missing folds for scalar select of {-1,0,1}Sanjay Patel2017-02-248-112/+72
| | | | | | | | | | | | | | | | | | | | | | | | The motivation for filling out these select-of-constants cases goes back to D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to: https://reviews.llvm.org/rL75531 https://reviews.llvm.org/rL159230 The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today: https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151 As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization: 1. Have DAGCombiner convert any select of constants into ext/add/not ops. 2 Have InstCombine canonicalize in the other direction (create more selects). Differential Revision: https://reviews.llvm.org/D30180 llvm-svn: 296137
* [libcxxabi] Disable calls to fprintf for baremetal targets.Ranjeet Singh2017-02-241-0/+2
| | | | | | | | | | We've been having issues with using libcxxabi and libunwind for baremetal targets because fprintf is dependent on io functions, this patch disables calls to fprintf when building for baremetal in release mode. Differential Revision: https://reviews.llvm.org/D30339 llvm-svn: 296136
* [libunwind] Disable calls to fprintf for baremetal targets.Ranjeet Singh2017-02-241-0/+11
| | | | | | | | | | We've been having issues with using libcxxabi and libunwind for baremetal targets because fprintf is dependent on io functions, this patch disables calls to fprintf when building for baremetal in release mode. Differential Revision: https://reviews.llvm.org/D30340 llvm-svn: 296135
* Recommit "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-249-154/+567
| | | | | | | | | | | | | | | | | | | | | | This time with the missing files. Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296134
* Revert "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-247-70/+154
| | | | | | This reverts r296132. I forgot to include the tests. llvm-svn: 296133
* [mips] Fix atomic compare and swap at O0.Simon Dardis2017-02-247-154/+70
| | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296132
* [globalisel] Decouple src pattern operands from dst pattern operands.Daniel Sanders2017-02-247-125/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
* [X86][SSE] Target shuffle combine can try to combine up to 16 vectorsSimon Pilgrim2017-02-241-6/+6
| | | | | | Noticed while profiling PR32037, the target shuffle ops were being stored in SmallVector<*,8> types but the combiner could store as many as 16 ops at maximum depth (2 per depth). llvm-svn: 296130
* [InstCombine] don't try SimplifyDemandedInstructionBits from zext/sext ↵Sanjay Patel2017-02-241-10/+0
| | | | | | | | | | | | | | | | | | | | because it's slow and unnecessary This one seems more obvious than D30270 that it can't make improvements because an extension always needs all of the incoming bits. There's one specific transform in SimplifyDemandedInstructionBits of converting a sext to a zext when the sign-bit is known zero, but that is handled explicitly in visitSext() with ComputeSignBit(). Like D30270, there are no IR differences (other than instruction names) for the case in PR32037: https://bugs.llvm.org//show_bug.cgi?id=32037 ...and no regression test differences. Zext/sext are a smaller part of the profile, but this still appears to shave off another 0.5% or so from 'opt -O2'. Differential Revision: https://reviews.llvm.org/D30280 llvm-svn: 296129
* [x86] use DAG.getAllOnesConstant(); NFCISanjay Patel2017-02-241-18/+11
| | | | llvm-svn: 296128
* Merge OutputSectionBase and OutputSection. NFC.Rafael Espindola2017-02-2420-317/+271
| | | | | | | Now that all special sections are SyntheticSections, we only need one OutputSection class. llvm-svn: 296127
* Fix missing call to base class constructor in r296121.Daniel Sanders2017-02-241-1/+3
| | | | | | | The 'Kind' member used in RTTI for InstructionPredicateMatcher was not initialized but went undetected since I always ended up with the correct value. llvm-svn: 296126
* [mips] Handle 64 bit immediate in and/or/xor pseudo instructions on mips64Simon Dardis2017-02-245-15/+555
| | | | | | | | | | | | | | | | | | | | Previously LLVM was assuming 32-bit signed immediates which results in and with a bitmask that has bit 31 set to incorrectly include bits 63-32 in the result. After applying this patch I can now compile all of the FreeBSD mips assembly code with clang. This issue also affects the nor, slt and sltu macros and I will fix those in a separate review. Patch By: Alexander Richardson Commit message reformatted by sdardis. Reviewers: atanasyan, theraven, sdardis Differential Revision: https://reviews.llvm.org/D30298 llvm-svn: 296125
* Delete trivial setter.Rafael Espindola2017-02-242-2/+1
| | | | llvm-svn: 296124
* Delete trivial getter.Rafael Espindola2017-02-244-25/+22
| | | | llvm-svn: 296123
* [ARM] GlobalISel: Select G_STOREDiana Picus2017-02-242-16/+70
| | | | | | Same as selecting G_LOAD. llvm-svn: 296122
* [globalisel] Sort RuleMatchers by priority.Daniel Sanders2017-02-241-2/+165
| | | | | | | | | | | | | | | | | | | | | | Summary: This makes more important rules have priority over less important rules. For example, '%a = G_ADD $b:s64, $c:s64' has priority over '%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the correct order by chance. NFC in this patch but it is required to make the next patch work correctly. Depends on D29710 Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka Reviewed By: ab, rovka Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29711 llvm-svn: 296121
* Minor test fixDiana Picus2017-02-241-2/+2
| | | | | | The test was using a size of 8 for loading/storing pointers. It should be 4. llvm-svn: 296120
* Hardware breakpoints for Linux on Arm/AArch64 targetsOmair Javaid2017-02-2420-140/+703
| | | | | | | | Please look at below differential link for upstream discussion. Differential revision: https://reviews.llvm.org/D29669 llvm-svn: 296119
* Delete unused enum values.Rafael Espindola2017-02-241-2/+0
| | | | llvm-svn: 296118
* Remove unnecessary template. NFC.Rafael Espindola2017-02-241-6/+5
| | | | llvm-svn: 296117
* Made test more target agnosticSerge Pavlov2017-02-241-0/+27
| | | | | | | Recommits r295975 (Added regression tests), reverted in r295975, because it did not work on non-X86 targets. llvm-svn: 296116
* [ARM] GlobalISel: Add reg bank mappings for storesDiana Picus2017-02-242-0/+45
| | | | | | Same as the ones for loads. llvm-svn: 296115
* Expand a comment. NFC.Rafael Espindola2017-02-241-1/+4
| | | | llvm-svn: 296114
* [change-namespace] fix asan failure in r296110.Eric Liu2017-02-241-8/+9
| | | | llvm-svn: 296113
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-0/+1
| | | | | | Attempt to fix failing test. llvm-svn: 296112
* Fixup r296105 - only run tests on MipsDiana Picus2017-02-241-0/+3
| | | | llvm-svn: 296111
* [change-namepsace] make it possible to whitelist symbols so they don't get ↵Eric Liu2017-02-246-2/+65
| | | | | | | | | | | | | | updated. Reviewers: hokein Reviewed By: hokein Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D30328 llvm-svn: 296110
* Fix signed/unsigned comparison warningsSimon Pilgrim2017-02-241-4/+4
| | | | llvm-svn: 296109
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-242-3/+49
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296108
* Attempt to fix windows unit testsPavel Labath2017-02-241-6/+6
| | | | | | | In LLVM r296049, IPDBSession::getGlobalScope lost its constness. Adjust the unittest to account for that. llvm-svn: 296107
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-0/+16
| | | | | | Corresponding test. llvm-svn: 296106
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-30/+21
| | | | | | | | | | | | | | Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
* Revert "[ARM] GlobalISel: Legalize stores"Diana Picus2017-02-242-42/+3
| | | | | | This reverts commit r296103 because the test broke on one of the bots. Sorry! llvm-svn: 296104
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-242-3/+42
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296103
* [APInt] Add APInt::setBits() method to set all bits in rangeSimon Pilgrim2017-02-245-9/+136
| | | | | | | | | | | | | | | | | | The current pattern for setting bits in range is typically: Mask |= APInt::getBitsSet(MaskSizeInBits, LoPos, HiPos); Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation memory for the temporary variable. This is one of the key compile time issues identified in PR32037. This patch adds the APInt::setBits() helper method which avoids the temporary memory allocation completely, this first implementation uses setBit() internally instead but already significantly reduces the regression in PR32037 (~10% drop). Additional optimization may be possible. I investigated whether there is need for APInt::clearBits() and APInt::flipBits() equivalents but haven't seen these patterns to be particularly common, but reusing the code would be trivial. Differential Revision: https://reviews.llvm.org/D30265 llvm-svn: 296102
* Implement QPassSignals GDB package in lldb-serverPavel Labath2017-02-2413-6/+228
| | | | | | | | | | | | | | | Summary: QPassSignals package allows lldb client to tell lldb-server to ignore certain types of signals and re-inject them back to inferior without stopping execution. Reviewers: jmajors, labath Subscribers: danalbert, srhines, emaste, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D30286 Author: Eugene Zemtsov <ezemtsov@google.com> llvm-svn: 296101
* [clang-tidy] Fix readability-redundant-declaration false positiveDaniel Marjamaki2017-02-242-17/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D27048 llvm-svn: 296100
* Fix crash when an incorrect redeclaration only differs in __unaligned ↵Roger Ferrer Ibanez2017-02-242-1/+6
| | | | | | | | | | | type-qualifier Fix an assertion that is hit when a redeclaration with differing types only differs in the unaligned type-qualifier. Differential Revision: https://reviews.llvm.org/D29986 llvm-svn: 296099
* Add clazy to external Clang examples pageKevin Funk2017-02-241-0/+5
| | | | | | | | | | Reviewers: silvas, rizsotto.mailinglist, sergio.martins Reviewed By: rizsotto.mailinglist Differential Revision: https://reviews.llvm.org/D30252 llvm-svn: 296098
* [ELF] - Implemented --no-dynamic-linker optionGeorge Rimar2017-02-243-3/+23
| | | | | | | | | | | | | | Feature is used for producing static-linked PIE executables (https://gcc.gnu.org/ml/gcc/2015-06/msg00008.html) And was implemented in GNU ld https://gcc.gnu.org/ml/gcc/2015-08/msg00099.html I also found it in linux kernel build system, though I think that x86/x64 bootloader does not really rely on it. Seems it used for PPC though. Differential revision: https://reviews.llvm.org/D30258 llvm-svn: 296097
* Add missing initialization for MachineOptimizationRemarkEmitterJustin Bogner2017-02-241-0/+1
| | | | | | This was missed in r293110. llvm-svn: 296096
* [WebAssembly] Add a README.txt entry for mergeable sections.Dan Gohman2017-02-241-0/+5
| | | | llvm-svn: 296095
* [AVX-512] Separate the fadd/fsub/fmul/fdiv/fmax/fmin with rounding mode ISD ↵Craig Topper2017-02-245-26/+38
| | | | | | opcodes into separate packed and scalar opcodes. This is more consistent with the rest of the ISD opcodes. NFC llvm-svn: 296094
* [ExecutionDepsFix] Use range-based for loop. NFCCraig Topper2017-02-241-2/+1
| | | | llvm-svn: 296093
* [IR][X86] Fix llvm version number in comments in AutoUpgrade. Forgot the ↵Craig Topper2017-02-241-13/+13
| | | | | | next release is 5.0 not 4.1 llvm-svn: 296092
* [AVX-512] Remove lzcnt intrinsics and autoupgrade them to generic ctlz ↵Craig Topper2017-02-248-96/+185
| | | | | | | | intrinsics with select. Clang has been emitting cltz intrinsics for a while now. llvm-svn: 296091
* [AVX-512] Move lzcnt and conflict intrinsic tests to avx512cd intrinsic test ↵Craig Topper2017-02-242-79/+77
| | | | | | file since that's their feature. llvm-svn: 296090
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