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* Remove duplicate entry for issue 3134Marshall Clow2018-11-131-1/+0
| | | | llvm-svn: 346772
* Update status for issue 3122Marshall Clow2018-11-131-2/+2
| | | | llvm-svn: 346771
* [AST][NFC] Pack DeclRefExprBruno Ricci2018-11-133-38/+37
| | | | | | | Move the SourceLocation to the bit-fields of Stmt + clang-format. This saves one pointer per DeclRefExpr but otherwise NFC. llvm-svn: 346770
* [CSP, Cloning] Update DuplicateInstructionsInSplitBetween to use DomTreeUpdater.Florian Hahn2018-11-136-51/+69
| | | | | | | | | | | | | | | | | | | | | This patch updates DuplicateInstructionsInSplitBetween to update a DTU instead of applying updates to the DT directly. Given that there only are 2 users, also updated them in this patch to avoid churn. I slightly moved the code in CallSiteSplitting around to reduce the places where we have to pass in DTU. If necessary, I could split those changes in a separate patch. This fixes missing DT updates when dealing with musttail calls in CallSiteSplitting, by using DTU->deleteBB. Reviewers: junbuml, kuhar, NutshellySima, indutny, brzycki Reviewed By: NutshellySima llvm-svn: 346769
* Revert "[ThinLTO] Internalize readonly globals"Steven Wu2018-11-1342-774/+89
| | | | | | This reverts commit 10c84a8f35cae4a9fc421648d9608fccda3925f2. llvm-svn: 346768
* [NFC][libcxx] Mark P1006R1 as completeLouis Dionne2018-11-131-1/+1
| | | | llvm-svn: 346767
* Implement P0972R0: <chrono> zero(), min(), and max() should be noexcept. ↵Marshall Clow2018-11-1310-26/+75
| | | | | | Reviewed as https://reviews.llvm.org/D53828 llvm-svn: 346766
* [NFC][libcxx] Mark P1006 as implemented in LLVM 8.0Louis Dionne2018-11-131-1/+1
| | | | | | It was implemented in https://reviews.llvm.org/D53867 llvm-svn: 346765
* [libcxx] Implement http://wg21.link/p1006, constexpr in pointer_traitsLouis Dionne2018-11-132-5/+16
| | | | | | | | | | | | | | | | Summary: P1006 adds support for constexpr in the specialization of pointer_traits for raw pointers. This is necessary in order to use pointer_traits in the upcoming constexpr containers. We expect P1006 to be voted into the working draft for C++20 at the San Diego meeting. Reviewers: mclow.lists, EricWF Subscribers: christof, dexonsmith, libcxx-commits Differential Revision: https://reviews.llvm.org/D53867 llvm-svn: 346764
* [libcxx] GNU/Hurd uses BSD-based interfaces, but does not (and won't) ↵Louis Dionne2018-11-131-2/+2
| | | | | | | | | | provide <sys/sysctl.h> Reviewed as https://reviews.llvm.org/D54338. Thanks to sthibaul for the patch. llvm-svn: 346763
* [InstCombine] add tests for funnel shift demanded bits; NFCSanjay Patel2018-11-131-0/+147
| | | | llvm-svn: 346762
* Fix uninitialized variable.Alexander Kornienko2018-11-131-1/+1
| | | | | | | | | | | | | | | | Flags variable was not initialized and later used (both isMBBSafeToOutlineFrom implementations assume it's initialized), which breaks test/CodeGen/AArch64/machine-outliner.mir. under memory sanitizer: MemorySanitizer: use-of-uninitialized-value #0 in llvm::AArch64InstrInfo::getOutliningType(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int) const llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:5494:9 #1 in (anonymous namespace)::InstructionMapper::convertToUnsignedVec(llvm::MachineBasicBlock&, llvm::TargetInstrInfo const&) llvm/lib/CodeGen/MachineOutliner.cpp:772:19 #2 in (anonymous namespace)::MachineOutliner::populateMapper((anonymous namespace)::InstructionMapper&, llvm::Module&, llvm::MachineModuleInfo&) llvm/lib/CodeGen/MachineOutliner.cpp:1543:14 #3 in (anonymous namespace)::MachineOutliner::runOnModule(llvm::Module&) llvm/lib/CodeGen/MachineOutliner.cpp:1645:3 #4 in (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1744:27 #5 in llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1857:44 #6 in compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:597:8 llvm-svn: 346761
* [CostModel][X86] Fix constant vector XOP rights shiftsSimon Pilgrim2018-11-133-89/+82
| | | | | | | | We'll constant fold these cases so they are as cheap as vector left shift cases. Noticed while improving funnel shift costs. llvm-svn: 346760
* [VectorUtils] Use namespace for InterleaveGroup template specialization.Florian Hahn2018-11-131-4/+6
| | | | llvm-svn: 346759
* [VPlan] VPlan version of InterleavedAccessInfo.Florian Hahn2018-11-136-49/+166
| | | | | | | | | | | | | | | | | This patch turns InterleaveGroup into a template with the instruction type being a template parameter. It also adds a VPInterleavedAccessInfo class, which only contains a mapping from VPInstructions to their respective InterleaveGroup. As we do not have access to scalar evolution in VPlan, we can re-use convert InterleavedAccessInfo to VPInterleavedAccess info. Reviewers: Ayal, mssimpso, hfinkel, dcaballe, rengolin, mkuper, hsaito Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D49489 llvm-svn: 346758
* [NFC] Move storage of dispatch-version to GlobalDeclErich Keane2018-11-1321-120/+182
| | | | | | | | | | | | | | | | | | | As suggested by Richard Smith, and initially put up for review here: https://reviews.llvm.org/D53341, this patch removes a hack that was used to ensure that proper target-feature lists were used when emitting cpu-dispatch (and eventually, target-clones) implementations. As a part of this, the GlobalDecl object is proliferated to a bunch more locations. Originally, this was put up for review (see above) to get acceptance on the approach, though discussion with Richard in San Diego showed he approved of the approach taken here. Thus, I believe this is acceptable for Review-After-commit Differential Revision: https://reviews.llvm.org/D53341 Change-Id: I0a0bd673340d334d93feac789d653e03d9f6b1d5 llvm-svn: 346757
* [clang-format] Do not treat the asm clobber [ as ObjCExprKrasimir Georgiev2018-11-132-2/+18
| | | | | | | | | | | | | | | | | Summary: The opening square of an inline asm clobber was being annotated as an ObjCExpr. This caused, amongst other things, the ObjCGuesser to guess header files containing that pattern as ObjC files. Reviewers: benhamilton Reviewed By: benhamilton Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D54111 llvm-svn: 346756
* [TTI] Make TargetTransformInfo::getOperandInfo static. NFCI.Simon Pilgrim2018-11-132-5/+4
| | | | | | It has no member dependencies and this makes it easier to reuse in other cost analysis code. llvm-svn: 346755
* [CostModel][X86] Add more cost tests for funnel shiftsSimon Pilgrim2018-11-132-8/+2853
| | | | | | Added full uniform/constant coverage for funnel shifts + rotates llvm-svn: 346754
* Fix comment for XOP rotates. NFCI.Simon Pilgrim2018-11-131-1/+1
| | | | llvm-svn: 346753
* Add bracket that was lost in rL346727 and has been causing buildbot failures ↵Simon Pilgrim2018-11-131-1/+1
| | | | | | for some time. llvm-svn: 346752
* Fix .cfi_restore with register numbers > 64Alexander Richardson2018-11-132-1/+23
| | | | | | | | | | | | | | | | | | | Summary: DW_CFA_restore can only encode register numbers up to 64 (6 bits unsigned int). For regsiter numbers > 64 we have to use DW_CFA_restore_extended instead which uses a ULEB128 value. I discovered this problem in the out-of-tree CHERI target since we use DWARF register number 89 for our return capability register. Reviewers: probinson, dblaikie, aprantl, espindola Reviewed By: dblaikie Subscribers: JohnReagan, emaste, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D54420 llvm-svn: 346751
* Fix modules build of AVRAsmParser.cppAlexander Richardson2018-11-131-3/+4
| | | | | | | | | | | | | | | | | Summary: Without this change I get the following error: lib/Target/AVR/AVRGenAsmMatcher.inc:1135:1: error: redundant #include of module 'LLVM_Utils.Support.Format' appears within namespace 'llvm' [-Wmodules-import-nested-redundant] Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53425 llvm-svn: 346750
* [ELF] - Renamed AArch64 specific relocations expressions. NFC.George Rimar2018-11-134-17/+18
| | | | | | They did not have AArch64 prefix. Now they do. llvm-svn: 346749
* UserManual: Tweak the /Zc:dllexportInlines- docs someHans Wennborg2018-11-132-9/+10
| | | | | | Addressing comments on https://reviews.llvm.org/D54319 llvm-svn: 346748
* [ELF] .gdb_index: fix CuOff when a .debug_info section contains more than 1 ↵Fangrui Song2018-11-132-9/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | DW_TAG_compile_unit Summary: Idx passed to readPubNamesAndTypes was an index into Chunks, not an index into the CU list. This would be incorrect if some .debug_info section contained more than 1 DW_TAG_compile_unit. In real world, glibc Scrt1.o is a partial link of start.os abi-note.o init.o and contains 2 CUs in debug builds. Without this patch, any application linking such Scrt1.o would have invalid .gdb_index The issue could be demonstrated by: (gdb) py print(gdb.lookup_global_symbol('main')) None Reviewers: espindola, ruiu Reviewed By: ruiu Subscribers: Higuoxing, grimar, dblaikie, emaste, aprantl, arichardson, JDevlieghere, arphaman, llvm-commits Differential Revision: https://reviews.llvm.org/D54361 llvm-svn: 346747
* [SystemZ] Increase the number of VLREPsJonas Paulsson2018-11-134-0/+114
| | | | | | | | | | | | | | | If a loaded value is replicated it is best to combine these two operations into a VLREP (load and replicate), but isel will not produce this if the load has other users as well. This patch handles this by putting the other users of the load to use the REPLICATE 0-element instead of the load. This way the load has only the REPLICATE node as user, and we get a VLREP. Review: Ulrich Weigand https://reviews.llvm.org/D54264 llvm-svn: 346746
* [X86] Add more tests for -x86-experimental-vector-widening-legalizationCraig Topper2018-11-1313-1710/+37889
| | | | | | | | | | I'm looking into whether we can make this the default legalization strategy. Adding these tests to help cover the changes that will be necessary. This patch adds copies of some tests with the command line switch enabled. By making copies its easier to compare the two legalization strategies. I've also removed RUN lines from some of these tests that already had -x86-experimental-vector-widening-legalization llvm-svn: 346745
* Attempt to make benchmarks fall back to -std=c++1z when C++17 isn't supported.Eric Fiselier2018-11-131-1/+12
| | | | | | | | | | | | | The benchmarks currently require C++17, however Clang 3.9 doesn't support -std=c++17 while still supporting all the C++17 features needed to compile the benchmarks. This patch makes the benchmark build attempt to fall back to -std=c++1z when -std=c++17 isn't supported. See llvm.org/PR39629 llvm-svn: 346744
* Add emplace tests for multiset/unordered_multiset.Eric Fiselier2018-11-133-1/+46
| | | | | | | | This patch adds tests to ensure that multiset/unordered_multiset's emplace method correctly constructs the elements without any intervening constructions. llvm-svn: 346743
* [FileCheck] fixing docs buildbot - use proper code-block typeFedor Sergeev2018-11-131-1/+1
| | | | llvm-svn: 346740
* Fix PR39619 - iterator_traits isn't SFINAE-friendly enough. Thanks to Eric ↵Marshall Clow2018-11-133-1/+141
| | | | | | for the report llvm-svn: 346738
* [clang-cl] Do not allow using both /Zc:dllexportInlines- and /fallback flagTakuto Ikuta2018-11-134-11/+9
| | | | | | | | | | | | | | Summary: /Zc:dllexportInlines with /fallback may cause unexpected linker error. It is better to disallow compile rather than warn for this combination. Reviewers: hans, thakis Reviewed By: hans Subscribers: cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D54426 llvm-svn: 346733
* CMake: Deprecate using llvm-config to detect llvm installationTom Stellard2018-11-131-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: clang currently uses llvm-config to determine the installation paths for llvm's headers and binaries. clang is also using LLVM's cmake files to determine other information about the LLVM build, like LLVM_LIBDIR_SUFFIX, LLVM_VERSION_*, etc. Since the installation paths are also available via the cmake files, we can simplify the code by only relying on information from cmake about the LLVM install and dropping the use of llvm-config altogether. In addition to simplifying the code, the cmake files have more accurate information about the llvm installation paths. llvm-config assumes that the lib, bin, and cmake directories are always located in the same place relative to the path of the llvm-config executable. This can be wrong if a user decides to install headers, binaries or libraries to a non-standard location: e.g. static libraries installed to /usr/lib/llvm6.0/ This patch takes the first step towards dropping llvm-config by removing the automatic detection of llvm-config (users can still manually supply a path to llvm-config by passing -DLLVM_CONFIG=/usr/bin/llvm-config to cmake) and adding a deprecation warning when users try to use this option. Reviewers: chandlerc, beanz, mgorny, chapuni Subscribers: mehdi_amini, dexonsmith, cfe-commits Differential Revision: https://reviews.llvm.org/D51714 llvm-svn: 346732
* CMake: Replace open-coded find_packageTom Stellard2018-11-131-7/+2
| | | | | | | | | | | | Reviewers: beanz, mgorny Reviewed By: mgorny Subscribers: cfe-commits, chapuni, llvm-commits Differential Revision: https://reviews.llvm.org/D32577 llvm-svn: 346731
* [BuildingAJIT] Fixing the build by inserting a forgotten paren.George Karpenkov2018-11-131-1/+1
| | | | llvm-svn: 346730
* [commit test] Add blank line to test/tools/llvm-objdump/full-contents.testXing GUO2018-11-131-0/+1
| | | | llvm-svn: 346729
* [DAGCombiner] Enable tryToFoldExtendOfConstant to run after legalize vector opsCraig Topper2018-11-131-14/+7
| | | | | | | | | | It should be ok to create a new build_vector after legal operations so long as it doesn't cause an infinite loop in DAG combiner. Unfortunately, X86's custom constant folding in combineVSZext is hiding any test changes from this. But I'm trying to get to a point where that X86 specific code isn't necessary at all. Differential Revision: https://reviews.llvm.org/D54285 llvm-svn: 346728
* [BuildingAJIT] Clang-format chapters 1 and 2.Lang Hames2018-11-134-14/+9
| | | | llvm-svn: 346727
* [BuildingAJIT] Update chapter 2 to use the ORCv2 APIs.Lang Hames2018-11-134-336/+273
| | | | llvm-svn: 346726
* [FileCheck] fixing small formatting error in docsFedor Sergeev2018-11-131-1/+1
| | | | llvm-svn: 346725
* [libObject] Fix getDesc for Elf_Note_ImplJake Ehrlich2018-11-133-37/+67
| | | | | | | This change fixes a bug in Elf_Note_Impl in which Elf_Word was used where uint8_t should have been used. llvm-svn: 346724
* [FileCheck] fixing typo in assertFedor Sergeev2018-11-131-1/+1
| | | | llvm-svn: 346723
* [FileCheck] introduce CHECK-COUNT-<num> repetition directiveFedor Sergeev2018-11-134-105/+293
| | | | | | | | | | | | | | | | | | | | | | | | In some cases it is desirable to match the same pattern repeatedly many times. Currently the only way to do it is to copy the same check pattern as many times as needed. And that gets pretty unwieldy when its more than count is big. Introducing CHECK-COUNT-<num> directive which acts like a plain CHECK directive yet matches the same pattern exactly <num> times. Extended FileCheckType to a struct to add Count there. Changed some parsing routines to handle non-fixed length of directive (all currently existing directives were fixed-length). The code is generic enough to allow future support for COUNT in more than just PlainCheck directives. See motivating example for this feature in reviews.llvm.org/D54223. Reviewed By: chandlerc, dblaikie Differential Revision: https://reviews.llvm.org/D54336 llvm-svn: 346722
* [MachineOutliner][NFC] Simplify isMBBSafeToOutlineFrom check in AArch64 outlinerJessica Paquette2018-11-131-20/+19
| | | | | | | | | Turns out it's way simpler to do this check with one LRU. Instead of maintaining two, just keep one. Check if each of the registers is available, and then check if it's a live out from the block. If it's a live out, but available in the block, we know we're in an unsafe case. llvm-svn: 346721
* Introduce DebugCounter into ConstProp passZhizhou Yang2018-11-131-26/+43
| | | | | | | | | | | | | | | | | | | Summary: This patch introduces DebugCounter into ConstProp pass at per-transformation level. It will provide an option to skip first n or stop after n transformations for the whole ConstProp pass. This will make debug easier for the pass, also providing chance to do transformation level bisecting. Reviewers: davide, fhahn Reviewed By: fhahn Subscribers: llozano, george.burgess.iv, llvm-commits Differential Revision: https://reviews.llvm.org/D50094 llvm-svn: 346720
* [InstCombine] add rotate variants that include select; NFCSanjay Patel2018-11-121-0/+84
| | | | llvm-svn: 346719
* [MachineOutliner][NFC] Change getMachineOutlinerMBBFlags to ↵Jessica Paquette2018-11-124-22/+44
| | | | | | | | | | | | isMBBSafeToOutlineFrom Instead of returning Flags, return true if the MBB is safe to outline from. This lets us check for unsafe situations, like say, in AArch64, X17 is live across a MBB without being defined in that MBB. In that case, there's no point in performing an instruction mapping. llvm-svn: 346718
* [llvm-objcopy] Don't copy Config when processing --keepFangrui Song2018-11-121-1/+1
| | | | llvm-svn: 346717
* [InstCombine] narrow width of rotate patterns, part 3Sanjay Patel2018-11-122-44/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a longer variant for the pattern handled in rL346713 This one includes zexts. Eventually, we should canonicalize all rotate patterns to the funnel shift intrinsics, but we need a bit more infrastructure to make sure the vectorizers handle those intrinsics as well as the shift+logic ops. https://rise4fun.com/Alive/FMn Name: narrow rotateright %neg = sub i8 0, %shamt %rshamt = and i8 %shamt, 7 %rshamtconv = zext i8 %rshamt to i32 %lshamt = and i8 %neg, 7 %lshamtconv = zext i8 %lshamt to i32 %conv = zext i8 %x to i32 %shr = lshr i32 %conv, %rshamtconv %shl = shl i32 %conv, %lshamtconv %or = or i32 %shl, %shr %r = trunc i32 %or to i8 => %maskedShAmt2 = and i8 %shamt, 7 %negShAmt2 = sub i8 0, %shamt %maskedNegShAmt2 = and i8 %negShAmt2, 7 %shl2 = lshr i8 %x, %maskedShAmt2 %shr2 = shl i8 %x, %maskedNegShAmt2 %r = or i8 %shl2, %shr2 llvm-svn: 346716
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