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* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-102-0/+17
| | | | llvm-svn: 192375
* Locate VS InstallDir in the presence of newer runtimeHans Wennborg2013-10-101-20/+19
| | | | | | | | | | | This fixes getSystemRegistryString() in WindowsToolChain.cpp to make sure that the VS version that it picks has an InstallDir. Previously we would look for the highest version os VS and check for InstallDir afterwards. Patch by Yaron Keren! llvm-svn: 192374
* <rdar://problem/14146606>Greg Clayton2013-10-102-8/+60
| | | | | | Fixed an issue where environment variables that contained special characters '$' and '#' would hose up the GDB server packet. We now use the QEnvironmentHexEncoded packet that has existed for a long time when we need to. Also added code that will stop sending the QEnvironmentHexEncoded and QEnvironment packets if they aren't supported. llvm-svn: 192373
* Removed the -t options from linking flags to avoid having the linker print ↵Greg Clayton2013-10-101-12/+0
| | | | | | out all .o files it was linking with. llvm-svn: 192372
* Provide msbuild integration for vs2013.Hans Wennborg2013-10-104-1/+49
| | | | | | Patch by Josh Samuel! llvm-svn: 192371
* Fix msbuild integration install script.Hans Wennborg2013-10-101-2/+5
| | | | | | | We previously failed to check whether the SUCCESS variable was set, and would thus always exit with a failure if vs2012 didn't exist. llvm-svn: 192370
* [ELF] Initial design to handle Linker scripts for ELF.Shankar Easwaran2013-10-103-3/+14
| | | | llvm-svn: 192369
* [test] Ignore failure for now for Darwin.Shankar Easwaran2013-10-101-0/+2
| | | | | | This is only a step to clean the buildbot. llvm-svn: 192368
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. llvm-svn: 192367
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
| | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. llvm-svn: 192365
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192364
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
| | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-103-0/+1406
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192362
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1015-3/+2827
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361
* [ELF] Return error from invalid linker script parse.Shankar Easwaran2013-10-103-2/+8
| | | | llvm-svn: 192360
* Disable RTTI in one test so clang doesn't assert behind the scenesTimur Iskhodzhanov2013-10-101-2/+2
| | | | llvm-svn: 192359
* POSIX dyld: handle extra MIPS link map fieldEd Maste2013-10-101-0/+15
| | | | | | | | On at least FreeBSD and NetBSD there is an extra field in the dyld link map struct. I've left an assert for other OSes (i.e., Linux/mips) until it's determined if they do the same. llvm-svn: 192358
* tsan: minor refactoringDmitry Vyukov2013-10-101-6/+1
| | | | | | Replace duplicate code snippet with function. llvm-svn: 192357
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Tim Northover2013-10-103-1406/+0
| | | | | | | | | class SIMD(lselem). " This reverts commit r192351. The LLVM side broke the build and the Clang tests will inevitably fail without it. llvm-svn: 192356
* tsan: add annotations to ignore synchronization operationsDmitry Vyukov2013-10-109-64/+161
| | | | | | | | The annotations are AnnotateIgnoreSyncBegin/End, may be useful to ignore some infrastructure synchronization that introduces lots of false negatives. llvm-svn: 192355
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-1015-2808/+3
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. llvm-svn: 192354
* Revert "Use aliases for more constructors and destructors."Rafael Espindola2013-10-102-34/+24
| | | | | | | | | This reverts commit r192300. The change itself looks correct, but it found issues on how we handle aliases in llvm. llvm-svn: 192353
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-1015-3/+2808
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192352
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-103-0/+1406
| | | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}. E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}. llvm-svn: 192351
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
| | | | llvm-svn: 192350
* Correctly detect colon in bit fields. Fixes PR17333.Alexander Kornienko2013-10-103-4/+10
| | | | | | | | | | | | | | Summary: Colon was incorrectly detected as a start of inheritance list. Fixed. Reviewers: djasper Reviewed By: djasper CC: cfe-commits, klimek Differential Revision: http://llvm-reviews.chandlerc.com/D1884 llvm-svn: 192349
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
| | | | llvm-svn: 192348
* Parser: Avoid a crash-on-invalid when trying to diagnose function calls with ↵Benjamin Kramer2013-10-102-2/+7
| | | | | | | | -> in it. Use the existing convenience function. llvm-svn: 192347
* Sema: Taking the address of a dtor is illegal per C++ [class.dtor]p2.Benjamin Kramer2013-10-103-0/+10
| | | | | | Emit a proper error instead of crashing in CodeGen. PR16892. llvm-svn: 192345
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-102-0/+117
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 llvm-svn: 192344
* [Mips] Support FSF Mips toolchain directories tree in the Clang driver.Simon Atanasyan2013-10-10373-25/+1541
| | | | | | | The patch reviewed by Rafael Espindola. http://llvm-reviews.chandlerc.com/D1843 llvm-svn: 192343
* [PECOFF] Add files appear in .drectve to input graphRui Ueyama2013-10-103-33/+70
| | | | | | | | -- so that command line options to specify new input files, such as /defaultlib:foo, is handled properly. Such options were ignored before this patch. llvm-svn: 192342
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-102-0/+6
| | | | llvm-svn: 192341
* Remove duplicate instructions.Craig Topper2013-10-101-16/+0
| | | | llvm-svn: 192340
* Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.Craig Topper2013-10-101-1/+1
| | | | llvm-svn: 192339
* Make test portable.Ted Kremenek2013-10-101-1/+1
| | | | llvm-svn: 192338
* Add a section about clang-cl to UsersManual.rstHans Wennborg2013-10-101-0/+108
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1881 llvm-svn: 192337
* POSIX RegisterContext for mips64Ed Maste2013-10-101-0/+58
| | | | | | | | | | | | Based on the POSIX x86_64 register context. This is sufficient for opening a mips64 (big endian) core file. Subsequent changes will connect the disassembler, dynamic loader support, ABI, etc. Review: http://llvm-reviews.chandlerc.com/D1873 (Missed "svn add" on this file in r192335) llvm-svn: 192336
* POSIX RegisterContext for mips64Ed Maste2013-10-1014-3/+795
| | | | | | | | | Based on the POSIX x86_64 register context. This is sufficient for opening a mips64 (big endian) core file. Subsequent changes will connect the disassembler, dynamic loader support, ABI, etc. Review: http://llvm-reviews.chandlerc.com/D1873 llvm-svn: 192335
* Fix getIntegerTypeOrder() to properly handle enums by first unwrapping their ↵Ted Kremenek2013-10-102-0/+39
| | | | | | | | | | | | underlying integer type. This is a precondition for calling getIntegerRank(). Fixes an assertion failure in a test case involving vectors. Fixes <rdar://problem/15091442> Please somebody check this. llvm-svn: 192334
* Fixed a leak of ASTStructExtractors and alsoSean Callanan2013-10-103-10/+8
| | | | | | | | | made sure we don't keep around no-longer-valid ASTTransformers. <rdar://problem/15182379> llvm-svn: 192333
* Merge RegisterContextPOSIX_x86_64 and RegisterContextPOSIX_i386 into ↵Michael Sartain2013-10-1019-874/+365
| | | | | | RegisterContextPOSIX_x86 llvm-svn: 192332
* Use KEY_WOW64_32KEY when reading the registry in WindowsToolChain.cpp (PR17033)Hans Wennborg2013-10-091-3/+6
| | | | | | | | This exposes a 32-bit view of the registry even when Clang is built as a 64-bit program. Since Visual Studio is a 32-bit application, this is necessary for us to find it. llvm-svn: 192331
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-093-17/+25
| | | | | | ins/ext. llvm-svn: 192330
* Revert "llvm-c: Make target initializer functions external functions in lib."Rui Ueyama2013-10-093-55/+36
| | | | | | | | This reverts commit r192316. The original change introduced circular dependencies between libTarget and backends. That would broke a build unless link everything into one big binary. llvm-svn: 192329
* Refine string literal concatenation warning within an NSArray literal to not ↵Ted Kremenek2013-10-092-4/+26
| | | | | | warn when the literal comes from a macro expansion. Fixes <rdar://problem/15147688>. llvm-svn: 192328
* Implemented the reverse-lookup API in the ASTSean Callanan2013-10-092-0/+17
| | | | | | | | | importer to avoid duplicate imports of anonymous structs. <rdar://problem/14421722> llvm-svn: 192327
* Initial checkin of curses-based LLDB UI (lui)Daniel Malea2013-10-0911-0/+1867
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLDB (Terminal) User Interface ============================== This directory contains the curses user interface for LLDB. To use it, ensure Python can find your lldb module. You may have to modify PYTHONPATH for that purpose: $ export PYTHONPATH=/path/to/lldb/module Then, run the lui.py. To load a core file: $ ./lui.py --core core To create a target from an executable: $ ./lui.py /bin/echo "hello world" To attach to a running process: $ ./lui.py --attach <pid> Known Issues ============ 1. Resizing the terminal will most likely cause lui to crash. 2. Missing paging in command-window 3. Only minimal testing (on Ubuntu Linux x86_64) Missing Features ================ - stdin/stdout/stderr windows - memory window - backtrace window - threads window - tab-completion - syntax-highlighting (via pygments library) - (local) variables window - registers window - disassembly window - custom layout llvm-svn: 192326
* patch by Yaron: Uses rand_s() from stdlib.h (when building for Windows)Marshall Clow2013-10-092-0/+28
| | | | llvm-svn: 192325
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