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* [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.Andrea Di Biagio2018-05-044-11/+13
| | | | | | | | | We don't need to pass the instruction index to the method that constructs new instruction descriptors. No functional change intended. llvm-svn: 331516
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-0415-182/+85
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [X86] Add test case for PR30290s failing behaviourJeremy Morse2018-05-041-0/+44
| | | | | | | | | Following the advice in review D45022, this currently tests for the broken llc output where an instruction is mis-scheduled. This test is committed in advance to improve the eventual fixing patch in D45022, making the bad behaviour that that patch fixes clearer. llvm-svn: 331514
* [ELF][AArch64] Add REQUIRES aarch64 to test [NFC]Peter Smith2018-05-041-0/+2
| | | | | | Forgot to add REQUIRES aarch64 to the test I recently added for D46255. llvm-svn: 331513
* Word wrap a test-file comment to 80 columnsJeremy Morse2018-05-041-3/+3
| | | | | | This is a test commit to check whether my account works. llvm-svn: 331512
* [ELF][AArch64] Implement the AArch64 TLSLD_LDST_LO12 family of relocsPeter Smith2018-05-042-0/+93
| | | | | | | | | | | | | | | | | Implement the following relocations for AArch64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC These are specified in ELF for the 64-bit Arm Architecture. Fixes pr36727 Differential Revision: https://reviews.llvm.org/D46255 llvm-svn: 331511
* [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCIBjorn Pettersson2018-05-042-40/+43
| | | | | | | | | | | | | | | | | | Summary: Added a helper method in RegsForValue to get a list with all the <RegNumber, RegSize> pairs that we want to iterate over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and in SelectionDAGBuilder::visitIntrinsicCall. Reviewers: vsk Reviewed By: vsk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46360 llvm-svn: 331510
* [RegUsageInfoCollector] Bugfix for handling of register aliases.Jonas Paulsson2018-05-042-7/+51
| | | | | | | | | | | | | | | | | Don't assume the alias of a defined reg is always already in the set. As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered, it is wrong to assume that all the aliases of the defined register in the *current function* is already present in the UsedPhysRegsMask. This patch changes this so that any definition in the current function of a phys-reg always results in all its aliases inserted into the set of defined registers. Review: Quentin Colombet https://reviews.llvm.org/D45157 llvm-svn: 331509
* [IRCE] Fix misuse of dyn_cast which leads to UBMax Kazantsev2018-05-041-2/+3
| | | | llvm-svn: 331508
* [XRay][compiler-rt] Support string-based config for Basic mode.Dean Michael Berris2018-05-048-28/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This addresses http://llvm.org/PR36790. This change allows the XRay Basic Mode implementation to use the string-based initialization routine provided through `__xray_log_init_mode(...)`. In the process, we've also deprecated some flags defined for the `XRAY_OPTIONS` environment variable. We then introduce another environment variable that can control the XRay Basic Mode implementation through `XRAY_BASIC_OPTIONS`. We also rename files from `xray_inmemory_log` to `xray_basic_logging` to be more in line with the mode implementation. Depends on D46174. Reviewers: echristo, kpw, pelikan, eizan Reviewed By: kpw Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46246 llvm-svn: 331507
* [XRay][compiler-rt] Support string-based config for FDR modeDean Michael Berris2018-05-049-59/+208
| | | | | | | | | | | | | | | | | | | | | | | | Summary: In this chage we add support for the string-based configuration mechanism for configuring FDR mode. We deprecate most of the `xray_fdr_log_*` flags that are set with the `XRAY_OPTIONS` environment variable. Instead we make the FDR implementation take defaults from the `XRAY_FDR_OPTIONS` environment variable, and use the flags defined in `xray_fdr_flags.{h,cc,inc}` for the options we support. This change addresses http://llvm.org/PR36790. Depends on D46173. Reviewers: eizan, pelikan, kpw, echristo Subscribers: llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D46174 llvm-svn: 331506
* [COFF] Implement the remaining ARM64 relocationsMartin Storsjo2018-05-044-10/+74
| | | | | | | | | | | Now only IMAGE_REL_ARM64_ABSOLUTE and IMAGE_REL_ARM64_TOKEN are unhandled. Also add range checks for the existing BRANCH26 relocation. Differential Revision: https://reviews.llvm.org/D46354 llvm-svn: 331505
* [Driver] Don't warn about unused inputs in config filesMartin Storsjo2018-05-043-4/+10
| | | | | | | | | This avoids warnings about unused linker parameters, just like other flags are ignored if they're from config files. Differential Revision: https://reviews.llvm.org/D46286 llvm-svn: 331504
* [XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).Dean Michael Berris2018-05-044-93/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This addresses http://llvm.org/PR36790. The change Deprecates a number of functions and types in `include/xray/xray_log_interface.h` to recommend using string-based configuration of XRay through the __xray_log_init_mode(...) function. In particular, this deprecates the following: - `__xray_set_log_impl(...)` -- users should instead use the `__xray_log_register_mode(...)` and `__xray_log_select_mode(...)` APIs. - `__xray_log_init(...)` -- users should instead use the `__xray_log_init_mode(...)` function, which also requires using the `__xray_log_register_mode(...)` and `__xray_log_select_mode(...)` functionality. - `__xray::FDRLoggingOptions` -- in following patches, we'll be migrating the FDR logging implementations (and tests) to use the string-based configuration. In later stages we'll remove the `__xray::FDRLoggingOptions` type, and ask users to migrate to using the string-based configuration mechanism instead. - `__xray::BasicLoggingOptions` -- same as `__xray::FDRLoggingOptions`, we'll be removing this type later and instead rely exclusively on the string-based configuration API. We also update the documentation to reflect the new advice and remove some of the deprecated notes. Reviewers: eizan, kpw, echristo, pelikan Reviewed By: kpw Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46173 llvm-svn: 331503
* [MachineCSE] Rewrite a loop checking if a block is in a set of blocks ↵Michael Zolotukhin2018-05-041-7/+5
| | | | | | | | | | | | | | | | | | without using a set. NFC. Summary: Using a set is unnecessary here an in some cases (see e.g. PR37277) takes significant amount of time to just insert values into it. In this particular case all we need is just to check if we find the block we are looking for or not. Reviewers: davide Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46411 llvm-svn: 331502
* Add children and child[N] properties to SBValue.i.Jim Ingham2018-05-042-17/+65
| | | | | | Also fixed some bad formatting in SBValue.i. llvm-svn: 331501
* [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.Craig Topper2018-05-041-4/+4
| | | | | | Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr. llvm-svn: 331500
* [LoopIdiomRecognize] Use a regular array instead of a SmallVector and ↵Craig Topper2018-05-041-2/+1
| | | | | | explicit ArrayRef. llvm-svn: 331499
* [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.Craig Topper2018-05-041-2/+2
| | | | | | These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong. llvm-svn: 331498
* The on-ios-device command line lldb has an optimization whereJason Molenda2018-05-042-30/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | when it and the inferior process both have the same shared cache (a conglomeration of all libraries at the same fixed address for all processes), lldb will read data out of its own memory to speed things up. The shared cache has a UUID, so lldb currently checks that the UUID of its own shared cache matches that of the inferior. This change adds one refinement to that -- it checks that the UUID is the same and that the base address of the shared cache is the same. And only uses its local shared cache if they are both identical. This involved using a different style of SPI with dyld to get lldb's shared cache load address, but it's not especially difficult. One unattractive part of the change is that I'm using the real underlying types of task_t and kern_return_t instead of picking them up from mach/mach.h. The defines that get picked up there (a lot from machine.h but others too) conflict with llvm/Support/MachO.h even when I have mach.h included before our SafeMachO.h which undefines most of the defines before including llvm/Support/MachO.h. I'll need to augment the #undefs in SafeMachO.h to get this to compile cleanly, but that'll be another day. <rdar://problem/39868238> llvm-svn: 331497
* [analyzer] NFC: Remove unused parameteer of StoreManager::CastRetrievedVal().Artem Dergachev2018-05-043-19/+7
| | | | llvm-svn: 331496
* [LoopIdiomRecognize] Add a test case to show incorrect transformation of an ↵Craig Topper2018-05-031-0/+82
| | | | | | | | | | | | | | | | | | | | infinite loop with side effets into a countable loop using ctlz. We currently recognize this idiom where x is signed and thus the shift in an ashr. int cnt = 0; while (x) { x >>= 1; // arithmetic shift right ++cnt; } and turn it into (bitwidth - ctlz(x)). And if there is anything else in the loop we will create a new loop that runs that many times. If x is initially negative, the shift result will never be 0 and thus the loop is infinite. If you put something with side effects in the loop, that side effect will now only happen bitwidth times instead of an infinite number of times. So this transform is only safe for logical shift right (which we don't currently recognize) or if we can prove that x cannot be negative before the loop. llvm-svn: 331493
* DWARFExpression: Convert file addresses to load addresses early on.Adrian Prantl2018-05-034-19/+30
| | | | | | | | | | | | | | | | | | This is a change that only affects Swift and is NFC for the language plugins on llvm.org. In Swift, we can have global variables with a location such as DW_OP_addr <addr> DW_OP_deref. The DWARF expression evaluator doesn't know how to apply a DW_OP_deref to a file address, but at the very end we convert the file address into a load address. This patch moves the file->load address conversion to right after the result of the DW_OP_addr is pushed onto the stack so that a subsequent DW_OP_deref (and potentially other operations) can be interpreted. rdar://problem/39767528 Differential revision: https://reviews.llvm.org/D46362 llvm-svn: 331492
* Revert "Follow-up to r331378. Update tests to allow to use C atomics in C++."Volodymyr Sapsai2018-05-033-3/+3
| | | | | | | | | | | | | It reverts commit r331484 because it caused test failures ThreadSanitizer-x86_64 :: Darwin/gcd-groups-destructor.mm ThreadSanitizer-x86_64 :: Darwin/libcxx-shared-ptr-stress.mm ThreadSanitizer-x86_64 :: Darwin/xpc-race.mm Foundation.h transitively includes <atomic>, so we have a case of benign mixing <stdatomic.h> and <atomic>. llvm-svn: 331491
* AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfoTom Stellard2018-05-035-9/+9
| | | | | | | | | | | | | | | | Summary: This makes is possible to have R600RegisterInfo and SIRegisterInfo not inherit from AMDGPURegisterInfo. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46280 llvm-svn: 331490
* [X86] Add WriteDPPD/WriteDPPS dot product scheduler classesSimon Pilgrim2018-05-0311-232/+42
| | | | llvm-svn: 331489
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-033-36/+34
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* Fix include of config.h that was incorrectly changed in r331184Justin Bogner2018-05-031-1/+1
| | | | | | | | | The RWMutex implementation depends on config.h macros (specifically HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be including it and not just llvm-config.h here or we fall back to a much slower implementation. llvm-svn: 331487
* [InstCombine] refine select-of-constants to bitwise opsSanjay Patel2018-05-034-214/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add logic for the special case when a cmp+select can clearly be reduced to just a bitwise logic instruction, and remove an over-reaching chunk of general purpose bit magic. The primary goal is to remove cases where we are not improving the IR instruction count when doing these select transforms, and in all cases here that is true. In the motivating 3-way compare tests, there are further improvements because we can combine/propagate select values (not sure if that belongs in instcombine, but it's there for now). DAGCombiner has folds to turn some of these selects into bit magic, so there should be no difference in the end result in those cases. Not all constant combinations are handled there yet, however, so it is possible that some targets will see more cmov/csel codegen with this change in IR canonicalization. Ideally, we'll go further to *not* turn selects into multiple logic/math ops in instcombine, and we'll canonicalize to selects. But we should make sure that this step does not result in regressions first (and if it does, we should fix those in the backend). The general direction for this change was discussed here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html Alive proofs for the new bit magic: https://rise4fun.com/Alive/XG7 Differential Revision: https://reviews.llvm.org/D46086 llvm-svn: 331486
* GlobalISel: Use a callback to compute constrained reg class for unallocatble ↵Tom Stellard2018-05-032-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | registers Summary: constrainOperandRegClass() currently fails if it tries to constrain the register class of an operand that is defeined with an unallocatable register class. This patch resolves this by adding a target callback to compute register constriants in this case. This is required by the AMDGPU because many of its instructions have source opreands defined with the unallocatable register classe VS_32 which is a union of two allocatable register classes VGPR_32 and SReg_32. Reviewers: dsanders, aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D45991 llvm-svn: 331485
* Follow-up to r331378. Update tests to allow to use C atomics in C++.Volodymyr Sapsai2018-05-033-3/+3
| | | | | | | | | | | | Reviewers: kubamracek Reviewed By: kubamracek Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D46363 llvm-svn: 331484
* [X86] Make __builtin_ia32_directstore_u32 and __builtin_ia32_movdir64b 'nothrow'Craig Topper2018-05-031-2/+2
| | | | | | These builtins snuck in while I was in the middle of adding nothrow to the other builtins in my local clone and I guess I missed them. llvm-svn: 331483
* [CodeGenFunction] Use the StringRef::split function that takes a char ↵Craig Topper2018-05-031-2/+2
| | | | | | | | separator instead of StringRef separator. NFC The char separator version should be a little better optimized. llvm-svn: 331482
* [ThinLTO] Add support for optimization remarks to thinBackendTeresa Johnson2018-05-032-16/+32
| | | | | | | | | | | | | | Summary: Support was added to the regular LTO backend, but not thinBackend. This patch adds that support. Reviewers: pcc, davide Subscribers: mehdi_amini, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D46376 llvm-svn: 331481
* Revert "DWARFExpression: Convert file addresses to load addresses early on."Adrian Prantl2018-05-034-32/+18
| | | | | | This reverts commit 331462 while investigating bot breakage. llvm-svn: 331480
* Add back condition that was accidentally removed in r331462.Adrian Prantl2018-05-031-3/+5
| | | | | | This should make the bots much happier. llvm-svn: 331479
* Added ThinLTO test to verify that index files are not generated if ↵Rumeet Dhindsa2018-05-031-0/+9
| | | | | | | | thinlto-index-only is not enabled. Differential Revision: https://reviews.llvm.org/D46405 llvm-svn: 331478
* [sanitizer] Remove unused 32-bit allocator TransferBatch parameterKostya Kortchinsky2018-05-032-3/+2
| | | | | | | | | | | | | | | | | Summary: NFC. Remove an unused parameter in `SizeClassAllocator32::TransferBatch::SetFromArray`, and thus get rid of the compilation warning. Reviewers: alekseyshl, vitalybuka Reviewed By: vitalybuka Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits Differential Revision: https://reviews.llvm.org/D46397 llvm-svn: 331477
* [PowerPC] add more FMF debug output; NFCSanjay Patel2018-05-031-3/+28
| | | | | | | | | We can't see all of the problems currently unless we look at debug output when the global 'unsafe' is on. It's a mess. This is another attempt to make sure that D45710 is not making changes unintentionally. llvm-svn: 331476
* Simplify test clang-tidy-__clang_analyzer__macro.cpp Zinovy Nis2018-05-031-5/+0
| | | | llvm-svn: 331475
* [clang-tidy] Define __clang_analyzer__ macro for clang-tidy for ↵Zinovy Nis2018-05-032-0/+22
| | | | | | | | | | | | | compatibility with clang static analyzer This macro is widely used in many well-known projects, ex. Chromium. But it's not set for clang-tidy, so for ex. DCHECK in Chromium is not considered as [[no-return]], and a lot of false-positive warnings about nullptr dereferenced are emitted. Differential Revision: https://reviews.llvm.org/D46325 llvm-svn: 331474
* [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class ↵Simon Pilgrim2018-05-032-17/+4
| | | | | | not SchedWriteVecALU. llvm-svn: 331473
* [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM ↵Simon Pilgrim2018-05-0318-661/+234
| | | | | | | | scheduler classes This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness. llvm-svn: 331472
* [PowerPC] add tests for FMF propagation; NFCSanjay Patel2018-05-031-0/+355
| | | | | | | | | | I'm choosing PPC out of convenience because it does all of the transforms of interest in these tests by default. There are multiple FMF problems shown in the current checks. D45710 is proposing to fix part of that. llvm-svn: 331471
* [ELF][MIPS] Check that a section has a valid reference to a file in the ↵Simon Atanasyan2018-05-032-9/+29
| | | | | | isMipsPIC routine llvm-svn: 331470
* [OPENMP] Fix test typos: CHECK-DAG-N -> CHECK-N-DAGJoel E. Denny2018-05-038-72/+72
| | | | | | | | Reviewed by: ABataev Differential Revision: https://reviews.llvm.org/D46370 llvm-svn: 331469
* Revert r331466: [OPENMP] Fix test typos: CHECK-DAG-N -> CHECK-N-DAG"Joel E. Denny2018-05-038-72/+72
| | | | | | Sorry, forgot to add commit log attributes. llvm-svn: 331468
* [WebAssembly] Add --stack-first option which places the shadow stack at ↵Sam Clegg2018-05-035-19/+85
| | | | | | | | | | start of linear memory Fixes https://bugs.llvm.org/show_bug.cgi?id=37181 Differential Revision: https://reviews.llvm.org/D46141 llvm-svn: 331467
* [OPENMP] Fix test typos: CHECK-DAG-N -> CHECK-N-DAGJoel E. Denny2018-05-038-72/+72
| | | | llvm-svn: 331466
* [DebugInfo] Correction for an assert in DIExpression::createFragmentExpressionBjorn Pettersson2018-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When we create a fragment expression, and there already is an old fragment expression, we assert that the new fragment is within the range for the old fragment. If for example the old fragment expression says that we describe bit 10-16 of a variable (Offset=10, Size=6), and we now want to create a new fragment expression only describing bit 3-6 of the original value, then the resulting fragment expression should have Offset=13, Size=3. The assert is supposed to catch if the resulting fragment expression is outside the range for the old fragment. However, it used to verify that the Offset+Size of the new fragment was smaller or equal than Offset+Size for the old fragment. What we really want to check is that Offset+Size of the new fragment is smaller than the Size of the old fragment. Reviewers: aprantl, vsk Reviewed By: aprantl Subscribers: davide, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D46391 llvm-svn: 331465
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