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* [LLDB] Fix a bunch of -Wdocumentation warnings in ExpressionParserJonas Devlieghere2019-11-136-111/+35
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* Remove redundant check. (NFC)Adrian Prantl2019-11-131-3/+0
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* Use cheaper, equivalent predicate. (NFC)Adrian Prantl2019-11-131-1/+1
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* [X86] Don't set the operation action for i16 SINT_TO_FP to Promote just ↵Craig Topper2019-11-133-45/+44
| | | | | | | because SSE1 is enabled. Instead do custom promotion in the handler so that we can still allow i16 to be used with fp80. And f64 without sse2.
* [X86] Fix typo in comment. NFCCraig Topper2019-11-131-1/+1
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* [X86] Move all the FP_TO_XINT/XINT_TO_FP setOperationActions into the same ↵Craig Topper2019-11-131-41/+28
| | | | | | | | | !useSoftFloat block. Qualify all of the Promote actions for these with !useSoftFloat too. NFCI The Promote action doesn't apply until LegalizeDAG. By the time we get there, we would have already softened all the FP operations if useSoftFloat was true. So there wouldn't be any operation left to Promote.
* Rename clang-module-related *DWO* functions to *ClangModule* (NFC)Adrian Prantl2019-11-135-46/+41
| | | | | | | This avoids confusing them with fission-related functionality. I also moved two accessor functions from DWARFDIE into static functions in DWARFASTParserClang were their only use is located.
* [PGO][PGSO] Temporarily disable the large working set size behavior.Hiroshi Yamauchi2019-11-132-2/+10
| | | | | | | | | | | | | | Summary: This temporarily disables the large working set size behavior in profile guided size optimization due to internal benchmark regressions. Reviewers: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70207
* libc++ status page: Fix HTML.Marek Kurdej2019-11-131-1/+1
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* [SimplifyCFG] add test for select with FMF; NFCSanjay Patel2019-11-131-6/+33
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* Rename ParseTypeFromDWO to ParseTypeFromClangModule (NFC)Adrian Prantl2019-11-132-26/+27
| | | | | Because that is what this function really does. The old name is misleading.
* Revert "[RISCV] Use compiler-rt if no GCC installation detected"Richard Smith2019-11-138-45/+19
| | | | | | | This change causes test failures for builds configured with -DCLANG_DEFAULT_RTLIB=compiler-rt. This reverts commit 3289352e6bb9d2949c678c625478024bf2a5fbfb.
* [SLP] fix miscompile on min/max reductions with extra uses (PR43948)Sanjay Patel2019-11-133-3/+16
| | | | | | | | | | | | | | | | | The bug manifests as replacing a reduction operand with an undef value. The problem appears to be limited to cases where a min/max reduction has extra uses of the compare operand to the select. In the general case, we are tracking "ExternallyUsedValues" and an "IgnoreList" of the reduction operations, but those may not apply to the final compare+select in a min/max reduction. For that, we use replaceAllUsesWith (RAUW) to ensure that the new vectorized reduction values are transferred to all subsequent users. Differential Revision: https://reviews.llvm.org/D70148
* [clang-format] refactor the use of the SMDiagnostics in replacement warningsmydeveloperday2019-11-131-40/+9
| | | | | | | | | | | | | | | | | Summary: Review comments in {D69854} recommended a simpler approach of creating the SMDiagnostics to remove much of the complexity. (thanks @thakis) @vlad.tsyrklevich I've rebuilt on both Windows and Linux (running Linux with Address and Undefined sanitizers) over the clang code base Reviewers: thakis, klimek, mitchell-stellar, vlad.tsyrklevich Reviewed By: thakis Subscribers: cfe-commits, thakis, vlad.tsyrklevich Tags: #clang-format, #clang Differential Revision: https://reviews.llvm.org/D69921
* [LLD] [COFF] Fix automatically importing data symbols from DLLs with LTOMartin Storsjö2019-11-132-2/+28
| | | | | | | | | | | | | | | | This broke in 51dcb292cc002, "[lld-link] diagnose undefined symbols before LTO when possible" (very soon after the 9.0 branch, so luckily the 9.0 release is unaffected). The code for loading objects we believe might be needed for autoimport (loadMinGWAutomaticImports()) does run before the new reportUnresolvable() function, but it had a condition to only operate on symbols from regular object files. This condition came from resolveRemainingUndefines(), but as loadMinGWAutomaticImports() now has to operate before the LTO, it has to operate on undefineds from LTO objects as well. Differential Revision: https://reviews.llvm.org/D70166
* Add -disable-builtin option to optDimitry Andric2019-11-132-0/+40
| | | | | | | | | | | | | | | | | | Summary: The option allows to disable specific target library builtin functions, instead of -disable-simplify-libcalls, which disables all of them. This is a prerequisite for D70143, which fixes PR43081. Reviewers: xbolva00, spatel, jdoerfert, efriedma Reviewed By: efriedma Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70193
* [LLDB] Fix a bunch of -Wdocumentation warningsJonas Devlieghere2019-11-1353-404/+212
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* [dsymutil] Add -dump to llvm-bcanalyzer invocationsFrancis Visoiu Mistrih2019-11-132-4/+4
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* [TargetLowering] Increase the storage size of NumRegistersForVT to allow the ↵Craig Topper2019-11-132-2/+5
| | | | | | | | | | type break down for v256i1 and other types to be stored correctly v256i1 on X86 without avx512 breaks down to 256 i8 values when passed between basic blocks. But the NumRegistersForVT was sized at a byte for each VT. This results in 256 being stored as 0. This patch enlarges the type to 16 bits and adds an assert to ensure that no information is lost when the entry is stored. Differential Revision: https://reviews.llvm.org/D70138
* [mips] Reduce number of nested `if` statements. NFCSimon Atanasyan2019-11-131-8/+5
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* [mips] Add test to check ELF output for JAL XGOT expansion. NFCSimon Atanasyan2019-11-131-0/+216
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* [mips] Add tests to check `jal sym+offset`. NFCSimon Atanasyan2019-11-132-61/+401
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* [LiveInterval] Allow updating subranges with slightly out-dated IRQuentin Colombet2019-11-136-11/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During register coalescing, we update the live-intervals on-the-fly. To do that we are in this strange mode where the live-intervals can be slightly out-of-sync (more precisely they are forward looking) compared to what the IR actually represents. This happens because the register coalescer only updates the IR when it is done with updating the live-intervals and it has to do it this way because updating the IR on-the-fly would actually clobber some information on how the live-ranges that are being updated look like. This is problematic for updates that rely on the IR to accurately represents the state of the live-ranges. Right now, we have only one of those: stripValuesNotDefiningMask. To reconcile this need of out-of-sync IR, this patch introduces a new argument to LiveInterval::refineSubRanges that allows the code doing the live range updates to reason about how the code should look like after the coalescer will have rewritten the registers. Essentially this captures how a subregister index with be offseted to match its position in a new register class. E.g., let say we want to merge: V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32> We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32> overlap, i.e., by choosing a class where we can find "offset + 1 == 3". Put differently we align V2's sub3 with V1's sub1: V2: sub0 sub1 sub2 sub3 V1: <offset> sub0 sub1 This offset will look like a composed subregidx in the the class: V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> Now if we didn't rewrite the uses and def of V1, all the checks for V1 need to account for this offset to match what the live intervals intend to capture. Prior to this patch, we would fail to recognize the uses and def of V1 and would end up with machine verifier errors: No live segment at def. This could lead to miscompile as we would drop some live-ranges and thus, miss some interferences. For this problem to trigger, we need to reach stripValuesNotDefiningMask while having a mismatch between the IR and the live-ranges (i.e., we have to apply a subreg offset to the IR.) This requires the following three conditions: 1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1> 2. An update with Tuple registers with a possibility to coalesce the subreg index: e.g., v1.dsub_1 == v2.dsub_3 3. Subreg liveness enabled. looking at the IR to decide what is alive and what is not, i.e., calling stripValuesNotDefiningMask. coalescer maintains for the live-ranges information. None of the targets that currently use subreg liveness (i.e., the targets that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and and #2, so this patch also artificial enables subreg liveness for ARM, so that a nice test case can be attached.
* [TTI] Fix cast cost on vector types.Michael Liao2019-11-133-3/+27
| | | | - Only split vector types when both src and dst types are splittable.
* [llvm-bcanalyzer] Don't dump the contents if -dump is not passedFrancis Visoiu Mistrih2019-11-132-2/+14
| | | | | | With all the previous refactorings this slipped through and now we always dump the contents of the bitcode files, even if -dump is not passed.
* [AArch64][v8.3a] Add missing imp-defs on RETA*.Ahmed Bougacha2019-11-132-2/+3
| | | | | | | | | | | | | RETA always implicitly uses LR, unlike RET which merely has an alias that defaults it to LR. Additionally, RETA implicitly uses SP as well, which it uses as a discriminator to authenticate LR. This isn't usually noticeable, because RET_ReallyLR is used in most of the backend. However, the post-RA scheduler, if enabled, will cause miscompiles if the imp-uses are missing. While there, fix a typo in the lone affected testcase.
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-133-8/+25
| | | | | | The instruction definition has been retroactively expanded to allow for an alias for '[xN, 0]!' as '[xN]!'. That wouldn't make sense on LDR, but does for LDRA.
* [SLP] improve test readability; NFCSanjay Patel2019-11-131-6/+6
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* [BPF] fix clang test failure for bpf-attr-preserve-access-index-4.cYonghong Song2019-11-131-3/+3
| | | | | | | Depending on different cmake configures, clang may generate different IR name for slot variables. Let us use the regex instead of hard coding the name. I did the same for other bpf-attr-preserve-access-index tests with such an approach, but somehow did not do for this one.
* [RISCV] Use compiler-rt if no GCC installation detectedEdward Jones2019-11-138-19/+45
| | | | | | | | If a GCC installation is not detected, then this attempts to use compiler-rt and the compiler-rt crtbegin/crtend implementations as a fallback. Differential Revision: https://reviews.llvm.org/D68407
* Fix typo in DwarfDebug [NFC]David Stenberg2019-11-131-1/+1
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* Don't set LLVM_NO_DEAD_STRIP on AIXDavid Tenty2019-11-131-1/+1
| | | | | | | | | | | | | | | | | Summary: when building plugins, as AIX has symbols in it's standard library that must be garbage collected or we will see link errors. Export lists will handle this instead on AIX. Reviewers: stevewan, sfertile, jasonliu, xingxue, DiggerLin Reviewed By: DiggerLin Subscribers: mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70130
* [BPF] add missing attribute in pragma-attribute-supported-attributes-list.testYonghong Song2019-11-131-0/+1
| | | | | Add the newly supported BPF specific __attribute__((preserve_access_index) in the pragma-attribute-supported-attributes-list.test.
* [SLP] reduce code duplication for min/max vs. other reductions; NFCISanjay Patel2019-11-131-77/+31
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* [BPF] Add preserve_access_index attribute for record definitionYonghong Song2019-11-1313-8/+412
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a resubmission for the previous reverted commit 943436040121 with the same subject. This commit fixed the segfault issue and addressed additional review comments. This patch introduced a new bpf specific attribute which can be added to struct or union definition. For example, struct s { ... } __attribute__((preserve_access_index)); union u { ... } __attribute__((preserve_access_index)); The goal is to simplify user codes for cases where preserve access index happens for certain struct/union, so user does not need to use clang __builtin_preserve_access_index for every members. The attribute has no effect if -g is not specified. When the attribute is specified and -g is specified, any member access defined by that structure or union, including array subscript access and inner records, will be preserved through __builtin_preserve_{array,struct,union}_access_index() IR intrinsics, which will enable relocation generation in bpf backend. The following is an example to illustrate the usage: -bash-4.4$ cat t.c #define __reloc__ __attribute__((preserve_access_index)) struct s1 { int c; } __reloc__; struct s2 { union { struct s1 b[3]; }; } __reloc__; struct s3 { struct s2 a; } __reloc__; int test(struct s3 *arg) { return arg->a.b[2].c; } -bash-4.4$ clang -target bpf -g -S -O2 t.c A relocation with access string "0:0:0:0:2:0" will be generated representing access offset of arg->a.b[2].c. forward declaration with attribute is also handled properly such that the attribute is copied and populated in real record definition. Differential Revision: https://reviews.llvm.org/D69759
* Fix comment spelling {addresing -> addressing} (NFC)Matthew Malcomson2019-11-131-1/+1
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* [profile] Factor out logic for mmap'ing merged profile, NFCVedant Kumar2019-11-131-22/+51
| | | | | | | | | | | Split out the logic to get the size of a merged profile and to do a compatibility check. This can be shared with both the continuous+merging mode implementation, as well as the runtime-allocated counters implementation planned for Fuchsia. Lifted out of D69586. Differential Revision: https://reviews.llvm.org/D70135
* [InstCombine] propagate fast-math-flags (FMF) to select when inverting ↵Sanjay Patel2019-11-135-75/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fcmp+select As noted by the FIXME comment, this is not correct based on our current FMF semantics. We should be propagating FMF from the final value in a sequence (in this case the 'select'). So the behavior even without this patch is wrong, but we did not allow FMF on 'select' until recently. But if we do the correct thing right now in this patch, we'll inevitably introduce regressions because we have not wired up FMF propagation for 'phi' and 'select' in other passes (like SimplifyCFG) or other places in InstCombine. I'm not seeing a better incremental way to make progress. That said, the potential extra damage over the existing wrong behavior from this patch is very limited. AFAIK, the only way to have different FMF on IR in the same function is if we have LTO inlined IR from 2 modules that were compiled using different fast-math settings. As seen in the tests, we may actually see some improvements with this patch because adding the FMF to the 'select' allows matching to min/max intrinsics that were previously missed (in the common case, the 'fcmp' and 'select' should have identical FMF to begin with). Next steps in the transition: Make similar changes in instcombine as needed. Enable phi-to-select FMF propagation in SimplifyCFG. Remove dependencies on fcmp with FMF. Deprecate FMF on fcmp. Differential Revision: https://reviews.llvm.org/D69720
* DWARFDebugLoclists: Add an api to get the location lists of a DWARF unitPavel Labath2019-11-133-47/+45
| | | | | | | | | | | | | | | | | Summary: This avoid the need to duplicate the location lists searching logic in various users. The "inline location list dumping" code (which is the only user actually updated to handle DWARF v5 location lists) is switched to this method. After adding v4 location list support, I'll switch other users too. Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70084
* Remove commented out CHECK-NEXT to try and appease ↵Simon Pilgrim2019-11-131-1/+0
| | | | llvm-clang-x86_64-expensive-checks-win buildbot
* PowerPC - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-133-7/+7
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* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
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* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
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* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
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* Sparc - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-133-3/+3
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* PPCReduceCRLogicals - fix static analyzer warnings. NFCSimon Pilgrim2019-11-131-6/+6
| | | | | - Fix uninitialized variable warnings. - Fix null dereference warnings.
* SLPVectorizer - make comparison operators + isInSchedulingRegion constSimon Pilgrim2019-11-131-3/+3
| | | | Fixes cppcheck warnings.
* [clang][Tooling] Filter flags that generate output in SyntaxOnlyAdjusterKadir Cetinkaya2019-11-132-2/+48
| | | | | | | | | | | | | | | | | | Summary: Flags that generate output could result in failures when creating syntax only actions. This patch introduces initial logic for filtering out those. The first such flag is "save-temps", which saves intermediate files(bitcode, assembly, etc.) into a specified directory. Fixes https://github.com/clangd/clangd/issues/191 Reviewers: hokein Subscribers: ilya-biryukov, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70173
* [clangd] Add bool return type to Index::refs API.Haojian Wu2019-11-1312-25/+58
| | | | | | | | | | | | | | | | Summary: Similar to fuzzyFind, the bool indicates whether there are more xref results. Reviewers: ilya-biryukov Reviewed By: ilya-biryukov Subscribers: merge_guards_bot, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70139
* [InstCombine] Avoid moving ops that do restrict undef across shuffles.Florian Hahn2019-11-132-14/+35
| | | | | | | | | | | | | | | | | | | I think we have to be a bit more careful when it comes to moving ops across shuffles, if the op does restrict undef. For example, without this patch, we would move 'and %v, <0, 0, -1, -1>' over a 'shufflevector %a, undef, <undef, undef, 1, 2>'. As a result, the first 2 lanes of the result are undef after the combine, but they really should be 0, unless I am missing something. For ops that do fold to undef on undef operands, the current behavior should be fine. I've add conservative check OpDoesRestrictUndef, maybe there's a better existing utility? Reviewers: spatel, RKSimon, lebedev.ri Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D70093
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