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* [llvm-pdbutil] Add the ability to truncate stream purpose names.Zachary Turner2017-07-054-36/+83
| | | | | | | This will be useful for aligning fields to a fixed with in subsequent patches. llvm-svn: 307204
* [DependenceAnalysis] Make sure base objects are the same when comparing GEPsBrendon Cahoon2017-07-052-1/+82
| | | | | | | | | | | | | | | The dependence analysis was returning incorrect information when using the GEPs to compute dependences. The analysis uses the GEP indices under certain conditions, but was doing it incorrectly when the base objects of the GEP are aliases, but pointing to different locations in the same array. This patch adds another check for the base objects. If the base pointer SCEVs are not equal, then the dependence analysis should fall back on the path that uses the whole SCEV for the dependence check. This fixes PR33567. Differential Revision: https://reviews.llvm.org/D34702 llvm-svn: 307203
* Fix test case in pre-C++11 mode; address Aaron Ballman's code review.Douglas Gregor2017-07-052-3/+3
| | | | llvm-svn: 307202
* Fix one more reference to lit.util.capture()Michael Zolotukhin2017-07-052-2/+4
| | | | | | The capture method was removed in r306643. llvm-svn: 307201
* Added more info on silent master to the doc.Galina Kistanova2017-07-051-0/+3
| | | | llvm-svn: 307200
* [InstCombine] Use CmpInst::Predicate with m_Cmp instead of ↵Craig Topper2017-07-051-1/+1
| | | | | | | | ICmpInst::Predicate. NFC There isn't really an ICmpInst version so we're just accessing the CmpInst version through inheritance. llvm-svn: 307199
* [WebAssembly] Fix types for address taken functionsSam Clegg2017-07-057-40/+70
| | | | | | Differential Revision: https://reviews.llvm.org/D34966 llvm-svn: 307198
* Cope with Range-v3's CONCEPT_REQUIRES idiomDouglas Gregor2017-07-052-0/+60
| | | | llvm-svn: 307197
* Customize the SFINAE diagnostics for enable_if to provide the failed condition.Douglas Gregor2017-07-057-12/+165
| | | | | | | | | | | | | | | | | | | | When enable_if disables a particular overload resolution candidate, rummage through the enable_if condition to find the specific condition that caused the failure. For example, if we have something like: template< typename Iter, typename = std::enable_if_t<Random_access_iterator<Iter> && Comparable<Iterator_value_type<Iter>>>> void mysort(Iter first, Iter last) {} and we call "mysort" with "std::list<int>" iterators, we'll get a diagnostic saying that the "Random_access_iterator<Iter>" requirement failed. If we call "mysort" with "std::vector<something_not_comparable>", we'll get a diagnostic saying that the "Comparable<...>" requirement failed. llvm-svn: 307196
* [tablegen] Avoid creating temporary stringsAlexander Shaposhnikov2017-07-054-15/+10
| | | | | | | | | | | | | If a method / function returns a StringRef but the variable is of type const std::string& a temporary string is created (StringRef has a cast operator to std::string), which is a suboptimal behavior. Differential revision: https://reviews.llvm.org/D34994 Test plan: make check-all llvm-svn: 307195
* [WebAssembly] MC: Don't generate extra types for weak aliasSam Clegg2017-07-053-2/+13
| | | | | | | | | | Previously we were generating a void(void) function type for a weak alias. Update the weak-alias test case to catch this. Differential Revision: https://reviews.llvm.org/D34734 llvm-svn: 307194
* Add docs for -foptimization-record-file=Brian Gesiak2017-07-051-0/+13
| | | | | | | | | | | | | | Summary: The Clang option was previously not included in the User's Manual. Reviewers: anemet, davidxl, hfinkel Reviewed By: hfinkel Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D34928 llvm-svn: 307193
* Add a test for relocation addend on mips.Rafael Espindola2017-07-051-0/+21
| | | | | | | An lld test found a bug in a llvm patch I am working on. It is better to have test coverage for that in llvm too. llvm-svn: 307192
* Revert "Revert "Replace trivial use of external rc.exe by writing our own ↵Eric Beckmann2017-07-058-78/+145
| | | | | | | | .res file."" This reverts commit 8c8dce3b8f15d6ebaefc35ce88f15a85c8cdbd6e. llvm-svn: 307191
* Revert "Revert "Switch external cvtres.exe for llvm's own resource library.""Eric Beckmann2017-07-0512-61/+30
| | | | | | | | This reverts commit 165e578e47f1cd38191120aad23a9020fb5476dd. Forgot to run tests on this. llvm-svn: 307190
* Revert "Switch external cvtres.exe for llvm's own resource library."Eric Beckmann2017-07-0512-30/+61
| | | | | | | | | This reverts commit 600d52c278e123dd08bee24c1f00932b55add8de. This patch still seems to break CrWinClangLLD, reverting until I can find root problem. llvm-svn: 307189
* Revert "Replace trivial use of external rc.exe by writing our own .res file."Eric Beckmann2017-07-058-145/+78
| | | | | | | | | This patch still seems to break CrWinClangLLD, reverting this once more until I can discover root problem. This reverts commit 3dbbc8ce43be50ffde2b1c655c6d3a25796fe78b. llvm-svn: 307188
* [PDB] Add a test that verifies every known type record.Zachary Turner2017-07-0510-57/+627
| | | | | | | | | | | | | | We had a lot of one-off tests for this type and that type, or "every type that happens to be generated by this program I built". Eventually I got a bug report filed where we were crashing on a type that was not covered by any of these tests. So this test carefully constructs a minimal C++ program that will cause every type we support to be emitted. This ensures full coverage for type records. Differential Revision: https://reviews.llvm.org/D34915 llvm-svn: 307187
* [AMDGPU] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-07-052-48/+50
| | | | | | NFC llvm-svn: 307186
* [Power9] Disable removing extra swaps on P9.Sean Fertile2017-07-051-1/+3
| | | | | | | | | | | | On power 8 we sometimes insert swaps to deal with the difference between Little-Endian and Big-Endian. The swap removal pass is supposed to clean up these swaps. On power 9 we don't need this pass since we do not need to insert the swaps in the first place. Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34627 llvm-svn: 307185
* {DAGCombiner] Fold (rot x, 0) -> xSimon Pilgrim2017-07-052-1/+4
| | | | llvm-svn: 307184
* [X86] Test bitfield loadstore tests on i686 as wellSimon Pilgrim2017-07-051-89/+162
| | | | llvm-svn: 307182
* [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.Sean Fertile2017-07-052-1/+42
| | | | | | | Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34829 llvm-svn: 307180
* [DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions ↵Andrew Zhogin2017-07-053-10/+24
| | | | | | | | | | into one with combined shift operand. For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize. Differential revision: https://reviews.llvm.org/D12833 llvm-svn: 307179
* Merge createOrphanCommands into addOrphanSections.Rafael Espindola2017-07-053-23/+18
| | | | | | This is a bit simpler and avoids a walk over OutputSections. llvm-svn: 307178
* [X86][SSE] Dropped -mcpu from bitcast+setcc mask testsSimon Pilgrim2017-07-052-130/+130
| | | | | | Use triple and attribute only for consistency llvm-svn: 307176
* [Sema] Don't allow -Wunguarded-availability to be silenced with redeclsErik Pilkington2017-07-0513-148/+220
| | | | | | Differential revision: https://reviews.llvm.org/D33816 llvm-svn: 307175
* [Power9] Exploit vector extract with variable index.Tony Jiang2017-07-052-0/+259
| | | | | | | | | | | | | | | | This patch adds the exploitation for new power 9 instructions which extract variable elements from vectors: VEXTUBLX VEXTUBRX VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX Differential Revision: https://reviews.llvm.org/D34032 Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) llvm-svn: 307174
* Prefix the name of the calling host function in the name of callee GPU kernelSingapuram Sanjay Srivallabh2017-07-057-15/+23
| | | | | | | | | | | | | | | | | | | Summary: Provide more context to the name of a GPU kernel by prefixing its name with the host function that calls it. E.g. The first kernel called by `gemm` would be `FUNC_gemm_KERNEL_0`. Kernels currently follow the "kernel_#" (# = 0,1,2,3,...) nomenclature. This patch makes it easier to map host caller and device callee, especially when there are many kernels produced by Polly-ACC. Reviewers: grosser, Meinersbur, bollu, philip.pfaffe, kbarton! Reviewed By: grosser Subscribers: nemanjai, pollydev Tags: #polly Differential Revision: https://reviews.llvm.org/D33985 llvm-svn: 307173
* Address comments that escaped D33333Erich Keane2017-07-054-60/+62
| | | | | | | | Patch By: Jen Yu Differential Revision:https://reviews.llvm.org/D34671 llvm-svn: 307172
* Fix a bug in regex_Iterator where it would report zero-length matches ↵Marshall Clow2017-07-052-1/+19
| | | | | | forever. Reported as http://llvm.org/PR33681. Thanks to Karen Arutyunov for the report. llvm-svn: 307171
* [lldb] Add a testcase for MainThreadCheckerRuntime pluginKuba Mracek2017-07-054-0/+92
| | | | | | This adds a simple testcase for MainThreadCheckerRuntime. The tool (Main Thread Checker) is only available on Darwin, so the test also detects the presence of libMainThreadChecker.dylib and is skipped if the tool is not available. llvm-svn: 307170
* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-055-54/+441
| | | | | | | | | | | | | | | This patch adds on to the exploitation added by https://reviews.llvm.org/D33510. This now catches build vector nodes where the inputs are coming from sign extended vector extract elements where the indices used by the vector extract are not correct. We can still use the new hardware instructions by adding a shuffle to move the elements to the correct indices. I introduced a new PPCISD node here because adding a vector_shuffle and changing the elements of the vector_extracts was getting undone by another DAG combine. Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) Differential Revision: https://reviews.llvm.org/D34009 llvm-svn: 307169
* [globalisel][tablegen] Fix another unused variable warning introduced by r307159Daniel Sanders2017-07-051-1/+1
| | | | llvm-svn: 307168
* Use LoadedObjectInfoHelper to simplify/delegate the implementation of 'clone'David Blaikie2017-07-051-4/+1
| | | | llvm-svn: 307167
* DebugInfo: Generalize LoadedObjectInfoHelper from RuntimeDyldDavid Blaikie2017-07-055-21/+27
| | | | | | | | Make it usable by any class derived (even indirectly) from LoadedObjectInfo by allowing a custom base class to be specified and perfect forwarding to the ctor. llvm-svn: 307166
* [NFC] Fix breaking build by adding REQUIRES: pollyaccSiddharth Bhat2017-07-052-0/+4
| | | | llvm-svn: 307165
* [NFC] [ScopInfo] fix warning about construction orderSiddharth Bhat2017-07-051-2/+2
| | | | llvm-svn: 307164
* [PPCGCodeGeneration] Teach Polly to start using live range reordering.Siddharth Bhat2017-07-055-13/+243
| | | | | | | | | | | | | | | | | | | | Polly did not use PPCG's live range reordering feature. Teach PPCGCodeGeneration to use this. Documentation on this is sparse, so much of the code is conservative. We currently kill all phi nodes in a Scop by appending them to the must_kill map we pass to PPCG. I do not have a proof of correctness, but it seems to be intuitively correct. We also do not handle `array_order`, which, quoting PPCG, is: PPCG/gpu.h: "Order dependences on non-scalars." It seems to consist of RAW dependences between arrays. We need to pass this information for more complex privatization cases. Differential Revision: https://reviews.llvm.org/D34941 llvm-svn: 307163
* [ELF] Fix nullptr dereference when creating an error message for a synthetic ↵Sean Eveson2017-07-052-1/+13
| | | | | | | | section. Differential Revision: https://reviews.llvm.org/D34752 llvm-svn: 307162
* Fix assorted compiler warnings (mismatched signedness and printf specifiers)Pavel Labath2017-07-054-36/+31
| | | | llvm-svn: 307161
* Fix "process load" on new android targetsPavel Labath2017-07-054-9/+13
| | | | | | | | | | | | | | | Summary: On older android targets, we needed a dlopen rename workaround to get "process load" working. Since API 26 this is not required as the targets have a proper libdl so with the function names one would expect. To make this work I've had to remove the const qualifier from the GetLibdlFunctionDeclarations function (as now the declarations can depend on the connected target). Since I was already modifying the prototype (and the lower levels were already converted to StringRef) I took the oportunity to convert this function as well. llvm-svn: 307160
* [globalisel][tablegen] Finish fixing compile-time regressions by merging the ↵Daniel Sanders2017-07-055-477/+360
| | | | | | | | | | | | | | | | | | | | | | | matcher and emitter state machines. Summary: Also, made a few minor tweaks to shave off a little more cumulative memory consumption: * All rules share a single NewMIs instead of constructing their own. Only one will end up using it. * Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent GIM_RecordInsn from changing MIs[0]. Depends on D33764 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33766 llvm-svn: 307159
* [SLPVectorizer] Add an extra parameter to cancelScheduling function, NFCI.Dinar Temirbulatov2017-07-051-22/+23
| | | | llvm-svn: 307158
* [IndVarSimplify] Add AShr exact flags using induction variables ranges.David Green2017-07-052-2/+118
| | | | | | | | | | This adds exact flags to AShr/LShr flags where we can statically prove it is valid using the range of induction variables. This allows further optimisations to remove extra loads. Differential Revision: https://reviews.llvm.org/D34207 llvm-svn: 307157
* [SystemZ] Simplify handling of ISA revisionsUlrich Weigand2017-07-051-26/+22
| | | | | | | | | | This moves determination of the ISA revision from the CPU name to one single place, removing a bunch of duplicated code. It also makes the supported ISA revisions available as feature strings. No functional change. llvm-svn: 307156
* [SystemZ] Simplify handling of 128-bit multiply/divide instructionUlrich Weigand2017-07-057-106/+106
| | | | | | | | | | | Several integer multiply/divide instructions require use of a register pair as input and output. This patch moves setting up the input register pair from C++ code to TableGen, simplifying the whole process and making it more easily extensible. No functional change. llvm-svn: 307155
* [SystemZ] Small cleanups to SystemZScheduleZ13.tdUlrich Weigand2017-07-051-25/+36
| | | | | | | | | | Fixes a couple of whitespace errors, re-sorts the vector floating-point instructions to make them more easily extensible, and adds a missing pseudo instruction. No functional change. llvm-svn: 307154
* [Hexagon] Preclude non-memory test from being optimized away. NFC.Nirav Dave2017-07-0511-38/+38
| | | | llvm-svn: 307153
* [driver][mips] Use AddTargetFeature to check arguments and add feature ↵Simon Atanasyan2017-07-051-7/+2
| | | | | | flags. NFC llvm-svn: 307152
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