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llvm-svn: 210776
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Summary: Depends on D3957
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3958
llvm-svn: 210775
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I misunderstood where the message was being converted.
llvm-svn: 210774
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Differential Revision: http://reviews.llvm.org/D3866
llvm-svn: 210773
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llvm-svn: 210772
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FP64
Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().
Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.
Depends on D3956
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3957
llvm-svn: 210771
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Differential Revision: http://reviews.llvm.org/D4017
llvm-svn: 210770
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When I originally added node RDTSCP_DAG (r207127) I forgot to add
a string name for it in method 'getTargetNodeName'.
No functional change intended.
llvm-svn: 210769
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Looks like msvc has an asymmetrical operator ==.
llvm-svn: 210768
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llvm-svn: 210767
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Background:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-June/073707.html
llvm-svn: 210766
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llvm-svn: 210765
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llvm-svn: 210764
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available on MIPS32r6/MIPS64r6
Summary:
This patch updates both the assembler and the code generator.
MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused
multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted.
Depends on D3955
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3956
llvm-svn: 210763
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Summary:
This patch disables madd/maddu/msub/msubu in both the assembler and code
generator.
Depends on D3896
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3955
llvm-svn: 210762
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vectors.
This patch adds target combine rules to match:
- [AVX] Horizontal add/sub of packed single/double precision floating point
values from 256-bit vectors;
- [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors.
llvm-svn: 210761
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ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
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llvm-svn: 210759
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This begins to address cognitive dissonance caused by treating the Note
diagnostic level as a severity in the diagnostic engine.
No change in functionality.
llvm-svn: 210758
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for consistency with the other tests.
No functional changes.
llvm-svn: 210757
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There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.
llvm-svn: 210756
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In general this fixes ambiguity that can arise from using
a different namespace that declares the same symbols as
we do.
One example inside llvm would be:
createIndVarSimplifyPass(..);
Which can be found in:
llvm/Transforms/Scalar.h
and
polly/LinkAllPasses.h
llvm-svn: 210755
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llvm-svn: 210754
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Fixes #19976.
The error log does not contain an error, in case we reject a candidate
without generating a diagnostic message by using invalid<>(...). This is
the case for the top-level region of a function.
The patch comes without a test-case because adding a useful one requires
additional code just for triggering it. Before the patch it would only trigger,
if we try to print the CFG with Scop error annotations.
llvm-svn: 210753
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llvm-svn: 210752
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llvm-svn: 210751
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functional change.
llvm-svn: 210750
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Turns out MSVC doesn't like this. Sorry for the noise!
llvm-svn: 210749
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llvm-svn: 210748
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llvm-svn: 210747
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llvm-svn: 210746
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This is in preparation for removing make_error_code from the llvm namespace.
llvm-svn: 210745
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Thanks to Alp Toker for noticing.
llvm-svn: 210744
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llvm-svn: 210743
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This implements target-independent FastISel lowering for the stackmap intrinsic.
llvm-svn: 210742
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llvm-svn: 210741
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Sorry I missed these before.
llvm-svn: 210740
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The posix errno values are probably to the best thing to use for
describing parse errors.
This should also fix the mingw build.
llvm-svn: 210739
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Mechanical change converting some of the simpler for loops into range-based for
loops. NFC.
llvm-svn: 210738
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llvm-svn: 210737
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llvm-svn: 210736
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llvm-svn: 210735
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The verifier follows GlobalAlias operands so that it can detect cycles of
alias definitions. It was doing this in a way that caused it to also recurse
through initializers for the GlobalValue aliasees, and it would fail when
an initializer refers to a global that is a declaration and not a definition.
This patch causes it to stop recursing when it hits a global definition.
<rdar://problem/17277451>
llvm-svn: 210734
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llvm-svn: 210733
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llvm-svn: 210732
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llvm-svn: 210731
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llvm-svn: 210730
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llvm-svn: 210729
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llvm-svn: 210728
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Sorry, no testcase, just noticed while trying to remove llvm's system_error.h
llvm-svn: 210727
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