summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* [llgo] set function personality with SetPersonalityAndrew Wilkins2015-07-151-1/+2
| | | | | | | | | | | | | | | Summary: If a function requires a landing pad, set the personality function. Requires D11116. Reviewers: pcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11117 llvm-svn: 242290
* Expose setPersonalityFn to GoAndrew Wilkins2015-07-151-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add Value.SetPersonality to the Go bindings. The Go bindings' Builder.CreateLandingPad has been updated, removing the obsolete personality argument. Background The personality attribute was removed from LandingPadInst in r239940, and llvm::Function::setPersonalityFn introduced. There was no corresponding change to either the C API or Go bindings. The Go bindings were broken until r239940, but that change was just to ignore the personality argument. This broke llgo. Reviewers: majnemer, pcc Subscribers: deadalnix, llvm-commits, axw Differential Revision: http://reviews.llvm.org/D11116 llvm-svn: 242289
* [PPC] Disassemble little endian ppc instructions in the right byte orderBenjamin Kramer2015-07-152-8/+681
| | | | | | PR24122. The test is simply a byte swapped version of ppc64-encoding.txt. llvm-svn: 242288
* CFI: Add a default blacklist.Peter Collingbourne2015-07-153-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11095 llvm-svn: 242287
* CodeGen: Improve CFI type blacklisting mechanism.Peter Collingbourne2015-07-155-27/+74
| | | | | | | | | | We now use the sanitizer special case list to decide which types to blacklist. We also support a special blacklist entry for types with a uuid attribute, which are generally COM types whose virtual tables are defined externally. Differential Revision: http://reviews.llvm.org/D11096 llvm-svn: 242286
* [OPENMP] http://llvm.org/PR24121: canonical loop rejected when comparison ↵Alexey Bataev2015-07-152-4/+86
| | | | | | | | has implicit conversions or destruction Allow to use complex iterators expressions in loops for C++. llvm-svn: 242285
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-152-84/+96
| | | | | | | | -Implemented as a table lookup. Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242284
* Fix test to run under MSYS2 by disabling MSYS conversion of /C /TP /TC.Yaron Keren2015-07-151-2/+3
| | | | | | Thanks to Alexpux. llvm-svn: 242283
* Update test comment that it fails the same way on MSYS2.Yaron Keren2015-07-151-3/+4
| | | | llvm-svn: 242282
* [PM/AA] Fix *numerous* serious bugs in GlobalsModRef found byChandler Carruth2015-07-151-22/+31
| | | | | | | | | | | | | | | | | | | | | | | | | inspection. While we want to handle calls specially in this code because they should have been modeled by the call graph analysis that precedes it, we should *not* be re-implementing the predicates for whether an instruction reads or writes memory. Those are well defined already. Notably, at least the following issues seem to be clearly missed before: - Ordered atomic loads can "write" to memory by causing writes from other threads to become visible. Similarly for ordered atomic stores. - AtomicRMW instructions quite obviously both read and write to memory. - AtomicCmpXchg instructions also read and write to memory. - Fences read and write to memory. - Invokes of intrinsics or memory allocation functions. I don't have any test cases, and I suspect this has never really come up in the real world. But there is no reason why it wouldn't, and it makes the code simpler to do this the right way. While here, I've tried to make the loops significantly simpler as well and added helpful comments as to what is going on. llvm-svn: 242281
* [SDAG] Optimize unordered comparison in soft-float mode (patch by Anton ↵Alexey Bataev2015-07-156-74/+189
| | | | | | | | | | | Nadolskiy) Current implementation handles unordered comparison poorly in soft-float mode. Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero. Differential Revision: http://reviews.llvm.org/D10804 llvm-svn: 242280
* [PowerPC] Use the MachineCombiner to reassociate fadd/fmulHal Finkel2015-07-154-0/+491
| | | | | | | | | | | | | This is a direct port of the code from the X86 backend (r239486/r240361), which uses the MachineCombiner to reassociate (floating-point) adds/muls to increase ILP, to the PowerPC backend. The rationale is the same. There is a lot of copy-and-paste here between the X86 code and the PowerPC code, and we should extract at least some of this into CodeGen somewhere. However, I don't want to do that until this code is enhanced to handle FMAs as well. After that, we'll be in a better position to extract the common parts. llvm-svn: 242279
* [PowerPC] Extend physical register live range in PPCVSXFMAMutateHal Finkel2015-07-151-2/+15
| | | | | | | | | | | | | If the source of the copy that defines the addend is a physical register, then its existing live range may not extend to the FMA being mutated. Make sure we extend the live range of the register to meet the FMA because it will become its operand in this case. I don't have an independent test case, but it will be exposed by change to be committed shortly enabling the use of the machine combiner to do fadd/fmul reassociation, and will be covered by one of the associated regression tests. llvm-svn: 242278
* [MachineCombiner] Work with itinerariesHal Finkel2015-07-152-4/+15
| | | | | | | | | | | | MachineCombiner predicated its use of scheduling-based metrics on hasInstrSchedModel(), but useful conclusions can be drawn from pipeline itineraries as well. Almost all of the logic (except for resource tracking in preservesResourceLen) can be used if we have an itinerary, so enable it in that case as well. This will be used by the PowerPC backend in an upcoming commit. llvm-svn: 242277
* [AArch64] Fix problems in decoding generic MSR instructionsPetr Pavlu2015-07-152-0/+7
| | | | | | | | | Bitpatterns rejected by the decoder method of `MSR (immediate)` should be decoded as the `extended MSR (register)` instruction. Differential Revision: http://reviews.llvm.org/D7174 llvm-svn: 242276
* [PM/AA] Cleanup some loops to be range-based. NFC.Chandler Carruth2015-07-151-20/+19
| | | | llvm-svn: 242275
* [TableGen] Improve decoding options for non-orthogonal instructionsPetr Pavlu2015-07-157-34/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When FixedLenDecoder matches an input bitpattern of form [01]+ with an instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are mixed/variable bits) it passes the input bitpattern to a specific instruction decoder method which then makes a final decision whether the bitpattern is a valid instruction or not. This means the decoder must handle all possible values of the variable bits which sometimes leads to opcode rewrites in the decoder method when the instructions are not fully orthogonal. The patch provides a way for the decoder method to say that when it returns Fail it does not necessarily mean the bitpattern is invalid, but rather that the bitpattern is definitely not an instruction that is recognized by the decoder method. The decoder can then try to match the input bitpattern with other possible instruction bitpatterns. For example, this allows to solve a situation on AArch64 where the `MSR (immediate)` instruction has form: 1101 0101 0000 0??? 0100 ???? ???1 1111 but not all values of the ? bits are allowed. The rejected values should be handled by the `extended MSR (register)` instruction: 1101 0101 000? ???? ???? ???? ???? ???? The decoder will first try to decode an input bitpattern that matches both bitpatterns as `MSR (immediate)` but currently this puts the decoder method of `MSR (immediate)` into a situation when it must be able to decode all possible values of the ? bits, i.e. it would need to rewrite the instruction to `MSR (register)` when it is not `MSR (immediate)`. The patch allows to specify that the decoder method cannot determine if the instruction is valid for all variable values. The decoder method can simply return Fail when it knows it is definitely not `MSR (immediate)`. The decoder will then backtrack the decoding and find that it can match the input bitpattern with the more generic `MSR (register)` bitpattern too. Differential Revision: http://reviews.llvm.org/D7174 llvm-svn: 242274
* [X86][SSE] Added i686/SSE2 vector shift tests.Simon Pilgrim2015-07-153-34/+987
| | | | | | We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets. llvm-svn: 242273
* Fix comments for several methods, NFCAlexey Bataev2015-07-151-3/+4
| | | | llvm-svn: 242272
* Remove extra \brief comment, NFCAlexey Bataev2015-07-151-1/+0
| | | | llvm-svn: 242271
* AVX : Fix ISA disabling in case AVX512VL , some instructions should be ↵Igor Breger2015-07-153-30/+246
| | | | | | | | | | disabled only if AVX512BW present. Tests added. Differential Revision: http://reviews.llvm.org/D11122 llvm-svn: 242270
* Initial support for writing thin archives.Rafael Espindola2015-07-155-18/+45
| | | | llvm-svn: 242269
* Tidy-up test case from r242257.Michael Zolotukhin2015-07-151-5/+8
| | | | llvm-svn: 242268
* [vim] Update the syntax to mark REQUIRES lines and not talk aboutChandler Carruth2015-07-151-3/+3
| | | | | | | | | | | dejagnu. I wonder if it would be useful to handle FileCheck prefixes specially? Especially if we could get some error checking. Suggestions welcome. Patches more welcome as I have no idea what I'm doing with vim script.... llvm-svn: 242267
* [vim] Add the IR's comment prefix to the comments list. This allows vimChandler Carruth2015-07-151-0/+1
| | | | | | | | to intelligently wrap prose written in IR comment blocks. This has bothered me for roughly ever, and my fellow IRC denziens convinced me to fix it. llvm-svn: 242266
* Use enum instead of unsigned. NFC.Pete Cooper2015-07-152-2/+4
| | | | | | | | The unsigned opcode argument here was the result of BinaryOperator->getOpcode(). That returns a BinaryOps enum which is more accurate than passing around an unsigned. llvm-svn: 242265
* Use cast<> instead of dyn_cast to remove llvm_unreachable. NFC.Pete Cooper2015-07-151-4/+2
| | | | | | | | | | This code was checking if we are an ICmpInst or FCmpInst then throwing unreachable if we are neither. We must be one or the other, so use a cast on the FCmpInst case to ensure that we are that case. Then we can avoid having an unreachable but still catch an error if we ever had another subclass of CmpInst. llvm-svn: 242264
* Use another foreach loop. NFCPete Cooper2015-07-151-2/+1
| | | | llvm-svn: 242263
* Fix another little nit with detach and keep stopped, you have to checkJim Ingham2015-07-151-1/+2
| | | | | | both for packet success and that the response is OK. llvm-svn: 242262
* Use getAnyExtOrTrunc helper instead of manually doing ext/trunc check. NFC.Pete Cooper2015-07-151-14/+5
| | | | | | | The code here was doing exactly what is already in getAnyExtOrTrunc(). Just use that method instead. llvm-svn: 242261
* Use getZExtOrTrunc helper instead of manually doing zext/trunc check. NFC.Pete Cooper2015-07-152-4/+2
| | | | | | | The code here was doing exactly what is already in getZExtOrTrunc(). Just use that method instead. llvm-svn: 242260
* COFF: Fix base relocations for __imp_ symbols on x86.Rui Ueyama2015-07-153-1/+8
| | | | | | | | Because thunks for dllimported symbols contain absolute addresses on x86, they need to be relocated at load-time. This bug was a cause of crashes in DLL initialization routines. llvm-svn: 242259
* Documentation cleanup, mostly fixing summaries. No functional change intended.James Dennett2015-07-151-141/+136
| | | | llvm-svn: 242258
* [LoopUnrolling] Handle cast instructions.Michael Zolotukhin2015-07-152-0/+109
| | | | | | | | | During estimation of unrolling effect we should be able to propagate constants through casts. Differential Revision: http://reviews.llvm.org/D10207 llvm-svn: 242257
* Correct length of packet that GDBRemoteCommunicationClient::Detach Jason Molenda2015-07-151-1/+1
| | | | | | | | should send when detaching and leaving the remote process/system halted. Previously only the 'D' initial char was sent, which resumed the process like a normal detach. llvm-svn: 242256
* Change conditional to assert. NFC.Pete Cooper2015-07-151-3/+2
| | | | | | | | This code was breaking from the case statement if the getStoreSizeInBits() value was not a multiple of 0. Given that the implementation returns getStoreSize() * 8, it can only be a multiple of 8. llvm-svn: 242255
* Use getStoreSize() instead of getStoreSizeInBits()/8. NFC.Pete Cooper2015-07-151-2/+1
| | | | | | | | The calls here were both to getStoreSizeInBits() which multiplies by 8. We then immediately divided by 8. Calling getStoreSize() returns the values we need without the extra arithmetic. llvm-svn: 242254
* [modules] Switch to the normal reverse postorder visitation algorithm when ↵Richard Smith2015-07-152-80/+82
| | | | | | computing redeclaration chains. llvm-svn: 242253
* Use a range loop.Rafael Espindola2015-07-141-4/+2
| | | | llvm-svn: 242250
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-144-42/+39
| | | | llvm-svn: 242249
* Create a wrapper pass for BlockFrequencyInfo.Wei Mi2015-07-145-49/+80
| | | | | | | | | | | | This is useful when we want to do block frequency analysis conditionally (e.g. only in PGO mode) but don't want to add one more pass dependence. Patch by congh. Approved by dexonsmith. Differential Revision: http://reviews.llvm.org/D11196 llvm-svn: 242248
* docs/conf.py: bump version to 3.8Hans Wennborg2015-07-141-2/+2
| | | | llvm-svn: 242247
* [Sema] Don't emit "pure virtual" warning for fully qualified calls.Davide Italiano2015-07-146-8/+44
| | | | | | | | | | -fapple-kext is an exception because calls will still go through the vtable in that mode. Add a note to make the user aware of that. PR: 23215 Differential Revision: http://reviews.llvm.org/D10935 llvm-svn: 242246
* Fix Sphinx error about duplicate label in CommandLine.rst:1560 and ↵Hans Wennborg2015-07-141-1/+1
| | | | | | CoverageMappingFormat.rst llvm-svn: 242245
* Update cxx_dr_status.html after 3.7 branchHans Wennborg2015-07-142-13/+13
| | | | llvm-svn: 242244
* Small fix to ThreadPlanStepRange::DumpRanges to loggingJason Molenda2015-07-141-1/+1
| | | | | | output when stepping through multiple ranges. llvm-svn: 242243
* WebAssembly: fix build breakage.JF Bastien2015-07-147-12/+13
| | | | | | | | | | | | | | | Summary: processFunctionBeforeCalleeSavedScan was renamed to determineCalleeSaves and now takes a BitVector parameter as of rL242165, reviewed in http://reviews.llvm.org/D10909 WebAssembly is still marked as experimental and therefore doesn't build by default. It does, however, grep by default! I notice that processFunctionBeforeCalleeSavedScan is still mentioned in a few comments and error messages, which I also fixed. Reviewers: qcolombet, sunfish Subscribers: jfb, dsanders, hfinkel, MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D11199 llvm-svn: 242242
* Make the variable names match the name of the metadata they control.Tyler Nowicki2015-07-143-39/+38
| | | | | | Rename Vectorizer to Vectorize and VectorizeUnroll to InterleaveCount. llvm-svn: 242241
* docs/conf.py: update version to 3.8Hans Wennborg2015-07-141-2/+2
| | | | llvm-svn: 242240
* [PowerPC] Support symbolic targets in patchpointsHal Finkel2015-07-142-57/+86
| | | | | | | Follow-up r235483, with the corresponding support in PPC. We use a regular call for symbolic targets (because they're much cheaper than indirect calls). llvm-svn: 242239
OpenPOWER on IntegriCloud