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* Revert "[AArch64] Fix isLegalAddImmediate() to return true for valid ↵Geoff Berry2016-03-012-48/+2
| | | | | | | | | | negative values." Revert r262248 in an attempt to fix the clang-native-aarch64-full bot and to investigate a performance regression in SingleSource/Benchmarks/CoyoteBench/huffbench llvm-svn: 262388
* Revert "[mips] Promote the result of SETCC nodes to GPR width."Vasileios Kalintiris2016-03-0127-809/+601
| | | | | | | | | This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
* New file to track implementation status of new POWER9 instructionsKit Barton2016-03-011-0/+442
| | | | llvm-svn: 262386
* This patch adds doxygen comments for the intrinsincs in the header file ↵Ekaterina Romanova2016-03-011-0/+40
| | | | | | | | | | popcntintrin.h. The doxygen comments are automatically generated based on Sony's intrinsics documentation. Differential Revision: http://reviews.llvm.org/D17550 llvm-svn: 262385
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-0122-3/+79
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* TableGen: Add hasNoSchedulingInfo to instructionsMatthias Braun2016-03-014-2/+12
| | | | | | | | | | | | | This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information. This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs. Differential Revision: http://reviews.llvm.org/D17728 llvm-svn: 262383
* Reword a misleading comment discussing landingpads and SEHReid Kleckner2016-03-011-2/+4
| | | | | | SEH doesn't use landingpads anymore. llvm-svn: 262382
* [NVPTX] Annotate param loads/stores as mayLoad/mayStore.Justin Lebar2016-03-012-56/+68
| | | | | | | | | | | | | | | | | | Summary: Tablegen was unable to determine that param loads/stores were actually reading or writing from memory. I think this isn't a problem in practice for param stores, because those occur in a block right before we make our call. But param loads don't have to at the very beginning of a function, so should be annotated as mayLoad so we don't incorrectly optimize them. Reviewers: jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D17471 llvm-svn: 262381
* [NVPTX] Remove workaround for tablegen crash in NVPTXInstrInfo.td.Justin Lebar2016-03-011-28/+7
| | | | | | | | | | | | Summary: Looks like this was caused by a typo. Reviewers: jholewinski Subscribers: jholewinski, llvm-commits, tra Differential Revision: http://reviews.llvm.org/D17357 llvm-svn: 262380
* [MSVC Compat] Correctly handle finallys nested within finallysDavid Majnemer2016-03-014-9/+36
| | | | | | | | | We'd lose track of the parent CodeGenFunction, leading us to get confused with regard to which function a nested finally belonged to. Differential Revision: http://reviews.llvm.org/D17752 llvm-svn: 262379
* Fix -Wnon-virtual-dtor warningsReid Kleckner2016-03-012-2/+5
| | | | llvm-svn: 262378
* [ELF] - handle of command line options incompatible with -rGeorge Rimar2016-03-013-10/+25
| | | | | | | | | Patch handles the command line options incompatible with relocatable output. Differential revision: http://reviews.llvm.org/D17758 llvm-svn: 262377
* Fix an issue where fast math flags were dropped during scalarization.Owen Anderson2016-03-013-2/+52
| | | | | | | Most portions of InstCombine properly propagate fast math flags, but apparently the vector scalarization section was overlooked. llvm-svn: 262376
* [SCEVValidator] Remove redundant visit.Michael Kruse2016-03-011-3/+0
| | | | | | | SCEVAddRecExpr::getStart() is synonymous to SCEVAddRecExpr::getOperand(0) which will be visited in the following loop anyway. llvm-svn: 262375
* [SCEV] Minor cleanup: rename method, C++11'ify; NFCSanjoy Das2016-03-012-7/+5
| | | | llvm-svn: 262374
* [NVPTX] Use different, convergent MIs for convergent calls.Justin Lebar2016-03-016-56/+99
| | | | | | | | | | | | | | | | | | | | | | | Summary: Calls sometimes need to be convergent. This is already handled at the LLVM IR level, but it also needs to be handled at the MI level. Ideally we'd propagate convergence from instructions, down through the selection DAG, and into MIs. But this is Hard, and would affect optimizations in the SDNs -- right now only SDNs with two operands have any flags at all. Instead, here's a much simpler hack: Add new opcodes for NVPTX for convergent calls, and generate these when lowering convergent LLVM calls. Reviewers: jholewinski Subscribers: jholewinski, chandlerc, joker.eph, jhen, tra, llvm-commits Differential Revision: http://reviews.llvm.org/D17423 llvm-svn: 262373
* [NVPTX] Nix hack used to emit '{' and '}' for NVPTX calls.Justin Lebar2016-03-011-9/+3
| | | | | | | | | | | | Summary: Tablegen understands backslash as an escape char; that's sufficient. Reviewers: jholewinski Subscribers: llvm-commits, tra, jholewinski Differential Revision: http://reviews.llvm.org/D17432 llvm-svn: 262372
* [NVPTX] Reformat NVPTXInstrInfo.td, and add additional comments.Justin Lebar2016-03-011-1418/+1400
| | | | | | | | | | | | | | | Summary: Also simplify some of the embedded C++ logic. No functional changes. Reviewers: jholewinski Subscribers: llvm-commits, tra, jholewinski Differential Revision: http://reviews.llvm.org/D17354 llvm-svn: 262371
* [X86] Elide references to _chkstk for dynamic allocasDavid Majnemer2016-03-018-40/+67
| | | | | | | | | | | | | | | The _chkstk function is called by the compiler to probe the stack in an order consistent with Windows' expectations. However, it is possible to elide the call to _chkstk and manually adjust the stack pointer if we can prove that the allocation is fixed size and smaller than the probe size. This shrinks chrome.dll, chrome_child.dll and chrome.exe by a cummulative ~133 KB. Differential Revision: http://reviews.llvm.org/D17679 llvm-svn: 262370
* [ELF] - More direct implementation of edata/etextGeorge Rimar2016-03-011-8/+9
| | | | | | | | | | | | As was suggested in mails, this patch implements edata/etext symbols in a more direct way. It iterates through PT_LOADs. Result seems to be the same and equal to gold output. Differential revision: http://reviews.llvm.org/D17755 llvm-svn: 262369
* Move ObjectYAML code to a new library.Rafael Espindola2016-03-0120-21/+43
| | | | | | | It is only ever used by obj2yaml and yaml2obj. No point in linking it everywhere. llvm-svn: 262368
* fix function names; NFCSanjay Patel2016-03-011-157/+151
| | | | llvm-svn: 262367
* [ELF] - do not create special symbols when creating relocatable outputGeorge Rimar2016-03-012-3/+188
| | | | | | | | | | | | | __start_/__end_ <section-name> symbols and other specials like: preinit_array_start/end init_array_start/end fini_array_start/end should not be created by linker when creating relocatable files. Differential revision: http://reviews.llvm.org/D17774 llvm-svn: 262366
* [Verifier] Don't abort on invalid cleanupretsDavid Majnemer2016-03-012-1/+16
| | | | | | | Code in visitEHPadPredecessors assume a little too much about the validity of a cleanupret with an invalid cleanuppad operand. llvm-svn: 262364
* Fix breakage caused by r262360.Easwaran Raman2016-03-012-1/+2
| | | | llvm-svn: 262363
* Add the beginnings of an update API for preserving MemorySSADaniel Berlin2016-03-014-0/+211
| | | | | | | | | | | | | | | | | | | Summary: This adds the beginning of an update API to preserve MemorySSA. In particular, this patch adds a way to remove memory SSA accesses when instructions are deleted. It also adds relevant unit testing infrastructure for MemorySSA's API. (There is an actual user of this API, i will make that diff dependent on this one. In practice, a ton of opt passes remove memory instructions, so it's hopefully an obviously useful API :P) Reviewers: hfinkel, reames, george.burgess.iv Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17157 llvm-svn: 262362
* [DebugInfo] Dump CIE augmentation data as a list of hex bytesSimon Atanasyan2016-03-014-3/+35
| | | | | | | | | CIE augmentation data might contain non-printable characters. The patch prints the data as a list of hex bytes. Differential Revision: http://reviews.llvm.org/D17759 llvm-svn: 262361
* Metadata support for profile summary.Easwaran Raman2016-03-014-63/+372
| | | | | | | | This adds support to convert ProfileSummary object to Metadata and create a ProfileSummary object from metadata. This would allow attaching profile summary information to Module allowing optimization passes to use it. llvm-svn: 262360
* [PPC64][VSX] Add short, char, and bool data type for vec_vsx_ld and ↵Kit Barton2016-03-012-0/+228
| | | | | | | | | | | | | | | | | | | | vec_vsx_st intrinsics Issue: https://llvm.org/bugs/show_bug.cgi?id=26720 Fix compile error when building ffmpeg for PowerPC64LE because of some vec_vsx_ld/vec_vsx_st intrinsics are not supported by current clang. New added intrinsics: (vector) {signed|unsigned} {short|char} vec_vsx_ld: (total: 8) bool vec_vsx_ld: (total: 1) (vector) {signed|unsigned} {short|char} vec_vsx_st: (total: 8) bool vec_vsx_st: (total: 1) Total: 18 intrinsics Phabricator: http://reviews.llvm.org/D17637 llvm-svn: 262359
* DAGCombiner: Turn extract of bitcasted integer into truncateMatt Arsenault2016-03-013-7/+37
| | | | | | | This reduces the number of bitcast nodes and generally cleans up the DAG when bitcasting between integers and vectors everywhere. llvm-svn: 262358
* Add isScalarInteger helper to EVT/MVTMatt Arsenault2016-03-013-0/+18
| | | | llvm-svn: 262357
* AMDGPU/SI: Implement DS_PERMUTE/DS_BPERMUTE Instruction Definitions and ↵Changpeng Fang2016-03-016-0/+67
| | | | | | | | | | | | | | | | Intrinsics Summary: This patch impleemnts DS_PERMUTE/DS_BPERMUTE instruction definitions and intrinsics, which are new since VI. Reviewers: tstellarAMD, arsenm Subscribers: llvm-commits, arsenm Differential Revision: http://reviews.llvm.org/D17614 llvm-svn: 262356
* [CLANG][AVX512][BUILTIN] Adding PSRL{DI|QI}{128|256|512} builtinMichael Zuckerman2016-03-015-0/+316
| | | | | | Differential Revision: http://reviews.llvm.org/D17714 llvm-svn: 262355
* [libFuzzer] remove FuzzerSanitizerOptions.cppKostya Serebryany2016-03-012-18/+0
| | | | llvm-svn: 262354
* [LLVM][AVX512] PSRL{DI|QI} Change imm8 to intMichael Zuckerman2016-03-014-47/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D17713 llvm-svn: 262353
* [X86] Check that attribute parameters match for tail calls (PR26590)Hans Wennborg2016-03-013-4/+95
| | | | | | | | | | | | In the code below on 32-bit targets, x would previously get forwarded to g() without sign-extension to 32 bits as required by the parameter attribute. void g(signed short); void f(unsigned short x) { g(x); } llvm-svn: 262352
* fix documentation comments; NFCSanjay Patel2016-03-011-85/+74
| | | | llvm-svn: 262351
* Explicitly select IAS in new embed-bitcode.c test.Daniel Sanders2016-03-011-2/+2
| | | | | | | This should fix clang-cmake-mips builder since MIPS does not have IAS enabled by default (yet). llvm-svn: 262350
* Revert "calculate builtin_object_size if argument is a removable pointer"Petar Jovanovic2016-03-012-53/+6
| | | | | | | Revert r262337 as "check-llvm ubsan" step failed on sanitizer-x86_64-linux-fast buildbot. llvm-svn: 262349
* [ELF] - Create _DYNAMIC symbol for dynamic outputGeorge Rimar2016-03-0116-19/+137
| | | | | | | | | | | lld needs to provide _DYNAMIC symbol when creating a shared library both bfd and gold do that. This should fix the https://llvm.org/bugs/show_bug.cgi?id=26732 Differential revision: http://reviews.llvm.org/D17607 llvm-svn: 262348
* function names start with a lowercase letter; NFCSanjay Patel2016-03-011-12/+12
| | | | llvm-svn: 262347
* [AMDGPU] Remove unused disassembler code.Nikolay Haustov2016-03-011-2/+0
| | | | llvm-svn: 262346
* Fix BUILD_SHARED_LIBS build.Rafael Espindola2016-03-015-0/+13
| | | | llvm-svn: 262345
* Refactor duplicated code for linking with pthread.Rafael Espindola2016-03-017-24/+13
| | | | llvm-svn: 262344
* tsan: describe heap/data locations in GoDmitry Vyukov2016-03-016-31/+108
| | | | llvm-svn: 262343
* sanitizer_common: silence compiler warningDmitry Vyukov2016-03-011-0/+1
| | | | llvm-svn: 262342
* [cmake] Add a few more compiler-rt check-* targets for EXTERNAL_COMPILER_RTFilipe Cabecinhas2016-03-011-1/+2
| | | | llvm-svn: 262341
* [cmake] Try to appease the buildbots.Filipe Cabecinhas2016-03-011-1/+4
| | | | llvm-svn: 262340
* DWARFExpression: Don't resolve load address in DW_OP_plusTamas Berghammer2016-03-011-3/+3
| | | | | | | | | If we have a TargetLoadAddress on the top of the DWARF stack then a DW_OP_plus or a DW_OP_plus_ucons sholudn't dereference (resolve) it and then add the value to the dereferenced value but it should offset the load address by the specified constant. llvm-svn: 262339
* [AMDGPU] Fix build warnings.Nikolay Haustov2016-03-011-2/+2
| | | | llvm-svn: 262338
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