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* Avoid losing Hi part when expanding VAARG nodes on big endian machinesDaniel Cederman2018-07-162-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | Summary: If the high part of the load is not used the offset to the next element will not be set correctly. For example, on Sparc V8, the following code will read val2 from offset 4 instead of 8. ``` int val = __builtin_va_arg(va, long long); int val2 = __builtin_va_arg(va, int); ``` Reviewers: jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48595 llvm-svn: 337161
* [x86/SLH] Fix a bug where we would try to post-load harden non-GPRs.Chandler Carruth2018-07-162-13/+297
| | | | | | | | | | | | | | | | Found cases that hit the assert I added. This patch factors the validity checking into a nice helper routine and calls it when deciding to harden post-load, and asserts it when doing so later. I've added tests for the various ways of loading a floating point type, as well as loading all vector permutations. Even though many of these go to identical instructions, it seems good to somewhat comprehensively test them. I'm confident there will be more fixes needed here, I'll try to add tests each time as I get this predicate adjusted. llvm-svn: 337160
* MSan: minor fixes, NFCAlexander Potapenko2018-07-161-7/+6
| | | | | | | - remove an extra space after |ID| declaration - drop the unused |FirstInsn| parameter in getShadowOriginPtrUserspace() llvm-svn: 337159
* [AccelTable] Provide DWARF5AccelTableStaticData for dsymutil.Jonas Devlieghere2018-07-162-41/+115
| | | | | | | | | | | For dsymutil we want to store offsets in the accelerator table entries rather than DIE pointers. In addition, we need a way to communicate which CU a DIE belongs to. This patch provides support for both of these issues. Differential revision: https://reviews.llvm.org/D49102 llvm-svn: 337158
* [x86/SLH] Extract another small helper function, add better comments andChandler Carruth2018-07-161-23/+34
| | | | | | use better terminology. NFC. llvm-svn: 337157
* [AMDGPU][Waitcnt] Re-apply fix "comparison of integers of different signs" ↵Mark Searles2018-07-161-1/+1
| | | | | | | | | | build error" Re-apply "[AMDGPU][Waitcnt] fix "comparison of integers of different signs" build error"" ( fe0a456510131f268e388c4a18a92f575c0db183 ), which was inadvertantly reverted via 2b2ee080f0164485562593b1b87291a48cea4a9a . llvm-svn: 337156
* [MSan] factor userspace-specific declarations into createUserspaceApi(). NFCAlexander Potapenko2018-07-161-38/+53
| | | | | | | | | | This patch introduces createUserspaceApi() that creates function/global declarations for symbols used by MSan in the userspace. This is a step towards the upcoming KMSAN implementation patch. Reviewed at https://reviews.llvm.org/D49292 llvm-svn: 337155
* run post-RA hazard recognizer pass lateMark Searles2018-07-165-13/+59
| | | | | | | | | | | | | Memory legalizer, waitcnt, and shrink passes can perturb the instructions, which means that the post-RA hazard recognizer pass should run after them. Otherwise, one of those passes may invalidate the work done by the hazard recognizer. Note that this has adverse side-effect that any consecutive S_NOP 0's, emitted by the hazard recognizer, will not be shrunk into a single S_NOP <N>. This should be addressed in a follow-on patch. Differential Revision: https://reviews.llvm.org/D49288 llvm-svn: 337154
* Revert "[AMDGPU][Waitcnt] fix "comparison of integers of different signs" ↵Mark Searles2018-07-161-1/+1
| | | | | | | | build error" This reverts commit fe0a456510131f268e388c4a18a92f575c0db183. llvm-svn: 337153
* [Sema] Reword warning for constant captures that are not requiredBenjamin Kramer2018-07-162-8/+8
| | | | | | | | | This is one of the darker corners of C++, make it clear that this is about constants and rephrase it a bit. Before: lambda capture 'i' is not required to be captured for this use After: lambda capture of constant 'i' is not required for this use llvm-svn: 337152
* [Analyzer] Mark `SymbolData` parts of iterator position as live in program ↵Adam Balogh2018-07-161-21/+33
| | | | | | | | | | | | | | state maps Marking a symbolic expression as live is non-recursive. In our checkers we either use conjured symbols or conjured symbols plus/minus integers to represent abstract position of iterators, so in this latter case we also must mark the `SymbolData` part of these symbolic expressions as live to prevent them from getting reaped. Differential Revision: https://reviews.llvm.org/D48764 llvm-svn: 337151
* Add a test with __gcov_flush called before terminating the program.Marco Castelluccio2018-07-163-0/+43
| | | | | | Test for https://bugs.llvm.org/show_bug.cgi?id=38067. llvm-svn: 337150
* [MemorySSAUpdater] Remove deleted trivial Phis from active worksetAlexandros Lamprineas2018-07-163-9/+58
| | | | | | | | | | | | | Bug fix for PR37808. The regression test is a reduced version of the original reproducer attached to the bug report. As stated in the report, the problem was that InsertedPHIs was keeping dangling pointers to deleted Memory-Phis. MemoryPhis are created eagerly and sometimes get zapped shortly afterwards. I've used WeakVH instead of an expensive removal operation from the active workset. Differential Revision: https://reviews.llvm.org/D48372 llvm-svn: 337149
* [Sema] Add fixit for unused lambda capturesAlexander Shaposhnikov2018-07-166-12/+158
| | | | | | | | | | | | | This diff adds a fixit to suggest removing unused lambda captures in the appropriate diagnostic. Patch by Andrew Comminos! Test plan: make check-all Differential revision: https://reviews.llvm.org/D48845 llvm-svn: 337148
* [X86] Merge the FR128 and VR128 regclass since they have identical spill and ↵Craig Topper2018-07-1626-740/+753
| | | | | | | | | | alignment characteristics. This unfortunately requires a bunch of bitcasts to be added added to SUBREG_TO_REG, COPY_TO_REGCLASS, and instructions in output patterns. Otherwise tablegen seems to default to picking f128 and then we fail when something tries to get the register class for f128 which isn't always valid. The test changes are because we were previously mixing fr128 and vr128 due to contrainRegClass finding FR128 first and passes like live range shrinking weren't handling that well. llvm-svn: 337147
* [MinGW] Automatically mangle Windows-specific entry points as CMartin Storsjo2018-07-162-0/+31
| | | | | | | | | | | | | | This mangles entry points wmain, WinMain, wWinMain or DllMain as C functions, to match the ABI for these functions. We already did the same for these functions in MSVC mode, but we also should do the same in the Itanium ABI. This fixes PR38124. Differential Revision: https://reviews.llvm.org/D49354 llvm-svn: 337146
* [x86/SLH] Fix an unused variable warning in release builds afterChandler Carruth2018-07-161-0/+1
| | | | | | r337144. llvm-svn: 337145
* [x86/SLH] Teach speculative load hardening to correctly harden theChandler Carruth2018-07-163-17/+1047
| | | | | | | | | | | | | | | | | | | | | | indices used by AVX2 and AVX-512 gather instructions. The index vector is hardened by broadcasting the predicate state into a vector register and then or-ing. We don't even have to worry about EFLAGS here. I've added a test for all of the gather intrinsics to make sure that we don't miss one. A particularly interesting creation is the gather prefetch, which needs to be marked as potentially "loading" to get the correct behavior. It's a memory access in many ways, and is actually relevant for SLH. Based on discussion with Craig in review, I've moved it to be `mayLoad` and `mayStore` rather than generic side effects. This matches how we model other prefetch instructions. Many thanks to Craig for the review here. Differential Revision: https://reviews.llvm.org/D49336 llvm-svn: 337144
* [InstCombine] add more SPFofSPF foldingChen Zheng2018-07-164-71/+67
| | | | | | Differential Revision: https://reviews.llvm.org/D49238 llvm-svn: 337143
* [XRay][compiler-rt] Use `SANITIZER_CXX_ABI_LIBRARY` for XRay unit testsDean Michael Berris2018-07-161-2/+2
| | | | | | | | | | | | | | | | | | Summary: Fix a TODO in CMake config for XRay tests to use the detected C++ ABI library in the tests. Also make the tests depend on the llvm-xray target when built in-tree. Reviewers: kpw, eizan Reviewed By: eizan Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D49358 llvm-svn: 337142
* [InstCombine] fold icmp pred (sub 0, X) C for vector typeChen Zheng2018-07-163-27/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D49283 llvm-svn: 337141
* Recommit r335794 "Add support for generating a call graph profile from ↵Michael J. Spencer2018-07-1613-7/+339
| | | | | | Branch Frequency Info." with fix for removed functions. llvm-svn: 337140
* Prune empty directory.Joerg Sonnenberger2018-07-150-0/+0
| | | | llvm-svn: 337139
* [x86/SLH] Extract one of the bits of logic to its own function. NFC.Chandler Carruth2018-07-151-43/+48
| | | | | | | This is just a refactoring to start cleaning up the code here and make it more readable and approachable. llvm-svn: 337138
* [X86] Add custom execution domain fixing for 128/256-bit integer logic ↵Craig Topper2018-07-1528-1806/+1427
| | | | | | | | | | | | operations with AVX512F, but not AVX512DQ. AVX512F only has integer domain logic instructions. AVX512DQ added FP domain logic instructions. Execution domain fixing runs before EVEX->VEX. So if we have AVX512F and not AVX512DQ we fail to do execution domain switching of the logic operations. This leads to mismatches in execution domain and more test differences. This patch adds custom domain fixing that switches EVEX integer logic operations to VEX fp logic operations if XMM16-31 are not used. llvm-svn: 337137
* [X86] Add load patterns for cases where we select X86Movss/X86Movsd to blend ↵Craig Topper2018-07-151-0/+32
| | | | | | | | instructions. This allows us to fold the load during isel without waiting for the peephole pass to do it. llvm-svn: 337136
* [X86] Use 128-bit blends instead vmovss/vmovsd for 512-bit vzmovl patterns ↵Craig Topper2018-07-153-18/+45
| | | | | | to match AVX. llvm-svn: 337135
* [X86] Use 128-bit ops for 256-bit vzmovl patterns.Craig Topper2018-07-157-31/+46
| | | | | | | | 128-bit ops implicitly zero the upper bits. This should address the comment about domain crossing for the integer version without AVX2 since we can use a 128-bit VBLENDW without AVX2. The only bad thing I see here is that we failed to reuse an vxorps in some of the tests, but I think that's already known issue. llvm-svn: 337134
* [cmake] Fix libomptarget/test/CMakeLists.txtAzharuddin Mohammed2018-07-151-2/+2
| | | | | | | | | | | | | | | | | Summary: Should be variable name instead of variable reference. If the variable is somehow unset, it messes up the if condition expression and causes a CMake error. Reviewers: jlpeyton, AndreyChurbanov, Hahnfeld Reviewed By: Hahnfeld Subscribers: mgorny, llvm-commits, openmp-commits Differential Revision: https://reviews.llvm.org/D47221 llvm-svn: 337133
* [DAGCombiner] fix typo in comment; NFCSanjay Patel2018-07-151-1/+1
| | | | llvm-svn: 337132
* [InstCombine] Corrections in comments for division transformation (NFC)Sanjay Patel2018-07-151-3/+3
| | | | | | | | | | The actual code seems to be correct, but the comments were misleading. Patch by Aaron Puchert! Differential Revision: https://reviews.llvm.org/D49276 llvm-svn: 337131
* [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)Sanjay Patel2018-07-1510-68/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
* [InstSimplify] add fixme comment for PR37776; NFCSanjay Patel2018-07-151-0/+4
| | | | llvm-svn: 337129
* [AMDGPU] adjusted test checks because minnum with NaN gets simplifiedSanjay Patel2018-07-151-4/+5
| | | | | | | | This was improved with rL337127, but I missed the failure in this test. I'm not sure what the expected result will be, so I've generalized it and added a FIXME comment. llvm-svn: 337128
* [InstSimplify] fold minnum/maxnum with NaN argSanjay Patel2018-07-152-16/+16
| | | | | | | | | | | | | | | This fold is repeated/misplaced in instcombine, but I'm not sure if it's safe to remove that yet because some other folds appear to be asserting that the transform has occurred within instcombine itself. This isn't the best fix for PR37776, but it probably hides the bug with the given code example: https://bugs.llvm.org/show_bug.cgi?id=37776 We have another test to demonstrate the more general bug. llvm-svn: 337127
* [InstSimplify] add tests for minnum/maxnum; NFCSanjay Patel2018-07-151-0/+82
| | | | | | | | | | | This isn't the best fix for PR37776, but it probably hides the bug with the given code example: https://bugs.llvm.org/show_bug.cgi?id=37776 We have another test to demonstrate the more general bug. llvm-svn: 337126
* Run thread safety tests with both lock and capability attributes; NFC to the ↵Aaron Ballman2018-07-151-57/+59
| | | | | | | | analysis behavior. Patch thanks to Aaron Puchert. llvm-svn: 337125
* [llvm-mca] Regenerate X86 specific tests. NFCAndrea Di Biagio2018-07-1513-15/+15
| | | | | | Not all tests were correctly updated by the update script after r336797. llvm-svn: 337124
* [llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio2018-07-1511-130/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers. The goal of this patch is to improve the throughput analysis in llvm-mca for the case where instructions perform partial register writes. On x86, partial register writes are quite difficult to model, mainly because different processors tend to implement different register merging schemes in hardware. When the code contains partial register writes, the IPC (instructions per cycles) estimated by llvm-mca tends to diverge quite significantly from the observed IPC (using perf). Modern AMD processors (at least, from Bulldozer onwards) don't rename partial registers. Quoting Agner Fog's microarchitecture.pdf: " The processor always keeps the different parts of an integer register together. For example, AL and AH are not treated as independent by the out-of-order execution mechanism. An instruction that writes to part of a register will therefore have a false dependence on any previous write to the same register or any part of it." This patch is a first important step towards improving the analysis of partial register updates. It changes the semantic of RegisterFile descriptors in tablegen, and teaches llvm-mca how to identify false dependences in the presence of partial register writes (for more details: see the new code comments in include/Target/TargetSchedule.h - class RegisterFile). This patch doesn't address the case where a write to a part of a register is followed by a read from the whole register. On Intel chips, high8 registers (AH/BH/CH/DH)) can be stored in separate physical registers. However, a later (dirty) read of the full register (example: AX/EAX) triggers a merge uOp, which adds extra latency (and potentially affects the pipe usage). This is a very interesting article on the subject with a very informative answer from Peter Cordes: https://stackoverflow.com/questions/45660139/how-exactly-do-partial-registers-on-haswell-skylake-perform-writing-al-seems-to In future, the definition of RegisterFile can be extended with extra information that may be used to identify delays caused by merge opcodes triggered by a dirty read of a partial write. Differential Revision: https://reviews.llvm.org/D49196 llvm-svn: 337123
* [AVR] Document some public functionsDylan McKay2018-07-151-0/+2
| | | | llvm-svn: 337122
* [TableGen] std::move vectors into TreePatternNode.Craig Topper2018-07-152-10/+12
| | | | llvm-svn: 337121
* [TableGen] Remove what seems to be an unnecessary std::map copy.Craig Topper2018-07-151-9/+6
| | | | | | The comment says the copy was made so it could be destroyed in the following loop, but the original map wasn't used after the loop. llvm-svn: 337120
* [X86] Add some optsize patterns for 256-bit X86vzmovl.Craig Topper2018-07-152-0/+83
| | | | | | These patterns use VMOVSS/SD. Without optsize we use BLENDI instead. llvm-svn: 337119
* [CMake] Use correct variable as header install prefixPetr Hosek2018-07-151-2/+2
| | | | | | | | | | This variable is already set in CMakeLists.txt but it wasn't used which means that the headers get installed into a wrong location when the per target runtime directory option is being used. Differential Revision: https://reviews.llvm.org/D49345 llvm-svn: 337118
* [CMake] Use libc++ and compiler-rt for sanitizersPetr Hosek2018-07-151-1/+3
| | | | | | | | | When building runtimes for Linux as part of Fuchsia toolchain, use libc++ and compiler-rt for sanitizers. Differential Revision: https://reviews.llvm.org/D49331 llvm-svn: 337117
* [CMake] Change the flag to use compiler-rt builtins to booleanPetr Hosek2018-07-152-12/+9
| | | | | | | | | | | | This changes the name and the type to what it was prior to r333037 which matches the name of the flag used in other runtimes: libc++, libc++abi and libunwind. We don't need the type to be a string since there's only binary choice between libgcc and compiler-rt unlike in the case of C++ library where there're multiple options. Differential Revision: https://reviews.llvm.org/D49325 llvm-svn: 337116
* [CMake] Pass CMAKE_INSTALL_DO_STRIP to external projectsPetr Hosek2018-07-151-1/+1
| | | | | | | | | This is necessary to make install-<target>-stripped work for external projects such as runtimes. Differential Revision: https://reviews.llvm.org/D49335 llvm-svn: 337115
* [TableGen] Add some std::move to the PatternToMatch constructor.Craig Topper2018-07-151-1/+1
| | | | | | The are two vectors passed by value to the constructor. We should be able to move them into the object. llvm-svn: 337114
* [llvm-mca] Turn InstructionTables into a Stage.Matt Davis2018-07-144-77/+61
| | | | | | | | | | | | | | | | | Summary: This patch converts the InstructionTables class into a subclass of mca::Stage. This change allows us to use the Stage's inherited Listeners for event notifications. This also allows us to create a simple pipeline for viewing the InstructionTables report. I have been working on a follow on patch that should cleanup addView in InstructionTables. Right now, addView adds the view to both the Listener list and Views list. The follow-on patch addresses the fact that we don't really need two lists in this case. That change is not specific to just InstructionTables, so it will be a separate patch. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49329 llvm-svn: 337113
* [NFC][InstCombine] foldICmpWithLowBitMaskedVal(): update comments.Roman Lebedev2018-07-141-2/+3
| | | | | | | | All predicates are handled. There does not seem to be any other possible folds here. There are some more folds possible with inverted mask though. llvm-svn: 337112
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