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* [MCA] Remove unused fields from BottleneckAnalysis. NFCAndrea Di Biagio2019-05-313-15/+12
| | | | | | This should appease the buildbots. llvm-svn: 362251
* [analyzer] print() JSONify: ExplodedNode revisionCsaba Dabis2019-05-311-3/+3
| | | | | | | | | | | | | | | Summary: Revert node-ID removal. Reviewers: NoQ, xazax.hun, ravikandhadai, baloghadamsoftware, Szelethus Subscribers: szepet, rnkovacs, a.sidorin, mikhail.ramalho, donat.nagy, dkrupp, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62658 llvm-svn: 362249
* [CMake] Feed BUNDLE_PATH through llvm target wrappersChris Bieneman2019-05-311-4/+4
| | | | | | This feeds the new llvm_codsign BUNDLE_PATH option through from the llvm target wrapper functions, so that you can specify the BUNDLE_PATH on the target's codesign. llvm-svn: 362248
* [MIR-Canon] Don't do vreg skip for independent instructions if there are none.Puyan Lotfi2019-05-312-1/+3
| | | | | | | | | We don't want to create vregs if there is nothing to use them for. That causes verifier errors. Differential Revision: https://reviews.llvm.org/D62740 llvm-svn: 362247
* [MCA] Refactor class BottleneckAnalysis. NFCIAndrea Di Biagio2019-05-313-80/+406
| | | | | | | | | | | | | | | | | | | | The resource pressure distribution computation is now delegated by class BottleneckAnalysis to an instance of class PressureTracker. Class PressureTracker is also responsible for: - tracking users of processor resource units. - tracking the number of delay cycles caused by increases in backpressure. BottleneckAnalysis internally initializes a dependency graph. Each nodes represents an instruction in the input code sequence. Edges of the dependency graph are critical register/memory/resource dependencies. Dependencies are only added to the graph if they are seen as critical by backend pressure events. The DependencyGraph is currently unused. It is possible to print the dependency graph (see method DependencyGraph::dump()) for debugging purposes. The long term goal is to use the information stored by the dependency graph in order to do critical path computation. llvm-svn: 362246
* Replace 'default' in an enum-over-a-switch with the missing list.Erich Keane2019-05-311-1/+5
| | | | | | | This suppressed the Wswitch warning causing me to miss it and write an assertion failure. llvm-svn: 362245
* [Tests] Add tests for loop predication of loops w/ne latch conditionsPhilip Reames2019-05-311-0/+172
| | | | llvm-svn: 362244
* Suppress nothrow/Exception spec conflict warning when we dont know the ES.Erich Keane2019-05-312-7/+10
| | | | | | | In any situation where the Exception Spec isn't clear, suppress the warning to avoid false positives. llvm-svn: 362243
* [CVP] Simplify non-overflowing saturating add/subNikita Popov2019-05-312-9/+32
| | | | | | | | | | If we can determine that a saturating add/sub will not overflow based on range analysis, convert it into a simple binary operation. This is a sibling transform to the existing with.overflow handling. Differential Revision: https://reviews.llvm.org/D62703 llvm-svn: 362242
* Revert revert of r362112 with minor SystemZ test file corrections.Kevin P. Neal2019-05-313-1/+6512
| | | | | | | | | | | | | [FPEnv] Added a special UnrollVectorOp method to deal with the chain on StrictFP opcodes This change creates UnrollVectorOp_StrictFP. The purpose of this is to address a failure that consistently occurs when calling StrictFP functions on vectors whose number of elements is 3 + 2n on most platforms, such as PowerPC or SystemZ. The old UnrollVectorOp method does not expect that the vector that it will unroll will have a chain, so it has an assert that prevents it from running if this is the case. This new StrictFP version of the method deals with the chain while unrolling the vector. With this new function in place during vector widending, llc can run vector-constrained-fp-intrinsics.ll for SystemZ successfully. Submitted by: Drew Wock <drew.wock@sas.com> Reviewed by: Cameron McInally, Kevin P. Neal Approved by: Cameron McInally Differential Revision: https://reviews.llvm.org/D62546 llvm-svn: 362241
* [FormatEntity] Ignore ASCII escape sequences when colors are disabled.Jonas Devlieghere2019-05-315-13/+42
| | | | | | | | | This patch makes the FormatEntity honor the debugger's color settings by not inserting ASCII escape sequences when colors are disabled. Differential revision: https://reviews.llvm.org/D62714 llvm-svn: 362240
* [AMDGPU] Use InliningThresholdMultiplier for inline hintStanislav Mekhanoshin2019-05-312-1/+79
| | | | | | | | | | | | | | AMDGPU uses multiplier 9 for the inline cost. It is taken into account everywhere except for inline hint threshold. As a result we are penalizing functions with the inline hint making them less probable to be inlined than those without the hint. Defaults are 225 for a normal function and 325 for a function with an inline hint. Currently we have effective threshold 225 * 9 = 2025 for normal functions and just 325 for those with the hint. That is fixed by this patch. Differential Revision: https://reviews.llvm.org/D62707 llvm-svn: 362239
* [NFC][InstCombine] Add unary FNeg tests to fabs.llCameron McInally2019-05-311-0/+76
| | | | llvm-svn: 362238
* [PPC] Correctly adjust branch probability in PPCReduceCRLogicalsGuozhi Wei2019-05-314-7/+137
| | | | | | | | | | | | | | | | | | | | | In PPCReduceCRLogicals after splitting the original MBB into 2, the 2 impacted branches still use original branch probability. This is unreasonable. Suppose we have following code, and the probability of each successor is 50%. condc = conda || condb br condc, label %target, label %fallthrough It can be transformed to following, br conda, label %target, label %newbb newbb: br condb, label %target, label %fallthrough Since each branch has a probability of 50% to each successor, the total probability to %fallthrough is 25% now, and the total probability to %target is 75%. This actually changed the original profiling data. A more reasonable probability can be set to 70% to the false side for each branch instruction, so the total probability to %fallthrough is close to 50%. This patch assumes the branch target with two incoming edges have same edge frequency and computes new probability fore each target, and keep the total probability to original targets unchanged. Differential Revision: https://reviews.llvm.org/D62430 llvm-svn: 362237
* Suppress nothrow/exception spec conflict warning when ES is parsed.Erich Keane2019-05-312-1/+16
| | | | | | | | | | | | | | The previously added warning ended up causing false positives when nothrow was used on member functions, where the exception specification wasn't yet parsed. So, throw() and noexcept(true) both were incorrectly warning. There doesn't seem to be a good way to force these to be parsed to identify which they are (and likely should not be), so suppress the warning. For now, unevaluated/uninstantiated are left as warnings as I am not creative enough to find a reproducer that causes a false positive for either. llvm-svn: 362236
* [PPC64][test] Delete redundant labels from ppc64-relocs.sFangrui Song2019-05-311-80/+20
| | | | llvm-svn: 362235
* [NFC][InstCombine] Add unary FNeg tests to fcmp.llCameron McInally2019-05-311-0/+118
| | | | llvm-svn: 362234
* [MachinePipeliner][NFC] Add some debug log and statisticsJinsong Ji2019-05-311-12/+71
| | | | | | | | This is to add some log and statistics for debugging Differential Revision: https://reviews.llvm.org/D62165 llvm-svn: 362233
* Revise test case due to the change from CUDA 10+.Michael Liao2019-05-311-1/+1
| | | | llvm-svn: 362232
* [NFC][InstCombine] Add unary FNeg tests to fdiv.llCameron McInally2019-05-311-0/+118
| | | | llvm-svn: 362231
* [AMDGPU] Regenerate add/sub shrink constant tests for an upcoming patchSimon Pilgrim2019-05-311-45/+390
| | | | llvm-svn: 362230
* [AMDGPU] Regenerate CTLZ tests for an upcoming patchSimon Pilgrim2019-05-311-128/+1006
| | | | llvm-svn: 362229
* [UpdateTestChecks] Add support for -march=r600 to match existing ↵Simon Pilgrim2019-05-311-0/+1
| | | | | | -march=amdgcn support llvm-svn: 362228
* [NFC][InstCombine] Add unary FNeg tests to fma.llCameron McInally2019-05-311-0/+96
| | | | llvm-svn: 362227
* [clangd] Add missing license for rename.cpp, NFC.Haojian Wu2019-05-311-1/+9
| | | | llvm-svn: 362226
* Fix for PR42089, regression from r362119Erich Keane2019-05-312-1/+17
| | | | | | | | | The implementation of the NoThrow ExceptionSpecificationType missed a switch statement for forming the diagnostic when an out-of-line member redeclaration misses the exception specification. This patch adds the correct case statement. llvm-svn: 362225
* [llvm-readobj] - Remove excessive `dynamic.test`George Rimar2019-05-313-248/+0
| | | | | | | | | | | | | | | | | | | | | | | | | dynamic.test is a test that checks dumping of dynamic tags. It uses precompiled objects as inputs and it is completely excessive nowadays: Now we have elf-dynamic-tags-machine-specific.test and elf-dynamic-tags.test. (https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags-machine-specific.test) (https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags.test) First is used to check target specific tags and second tests the common flags. These tests use YAML, which is much better than using precompiled binaries. Note that new reviews tend to update the YAML based tests to add new tags, e.g. see D62596. With this patch it became possible to remove dynamic-table-so.aarch64 binary from the inputs folder. (other binaries are still used in other tests). Differential revision: https://reviews.llvm.org/D62728 llvm-svn: 362224
* gn build: Merge r362160Nico Weber2019-05-311-0/+1
| | | | llvm-svn: 362223
* gn build: Merge r362196Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362222
* gn build: Merge r362190Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362221
* [ELF] Delete GotEntrySize and GotPltEntrySizeFangrui Song2019-05-3112-35/+14
| | | | | | | | | | | | | GotEntrySize and GotPltEntrySize were added in D22288. Later, with the introduction of wordsize() (then Config->Wordsize), they become redundant, because there is no target that sets GotEntrySize or GotPltEntrySize to a number different from Config->Wordsize. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D62727 llvm-svn: 362220
* ftime-trace: Trace loop passesRussell Gallop2019-05-311-0/+3
| | | | | | | | | | These can take a significant amount of time in some builds. Suggested by Andrea Di Biagio. Differential Revision: https://reviews.llvm.org/D62666 llvm-svn: 362219
* [ELF] Replace a dead test in getSymVA() with assert()Fangrui Song2019-05-311-7/+1
| | | | | | | | | | | | Symbols relative to discarded comdat sections are Undefined instead of Defined now (after D59649 and D61583). The `== &InputSection::Discarded` test becomes dead. I cannot find a test related to this behavior. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62725 llvm-svn: 362218
* [InstCombine] 'C-(C2-X) --> X+(C-C2)' constant-foldRoman Lebedev2019-05-312-3/+8
| | | | | | | | | | It looks this fold was already partially happening, indirectly via some other folds, but with one-use limitation. No other fold here has that restriction. https://rise4fun.com/Alive/ftR llvm-svn: 362217
* [InstCombine] 'add (sub C1, X), C2 --> sub (add C1, C2), X' constant-foldRoman Lebedev2019-05-312-19/+18
| | | | | | https://rise4fun.com/Alive/qJQ llvm-svn: 362216
* [AArch64][SVE2] Asm: support WHILE instructionsCullen Rhodes2019-05-3114-0/+543
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62601 llvm-svn: 362215
* [AArch64][SVE2] Asm: support TBL/TBX instructionsCullen Rhodes2019-05-316-7/+181
| | | | | | | | | | | | | | | | | Summary: A three sources variant of the TBL instruction is added to the existing SVE instruction in SVE2. This is implemented with minor changes to the existing TableGen class. TBX is a new instruction with its own definition. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62600 llvm-svn: 362214
* [AArch64][SVE2] Asm: support SVE2 store instructionsCullen Rhodes2019-05-3111-2/+661
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * STNT1B, STNT1H, STNT1S, STNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62599 llvm-svn: 362213
* [MIPS GlobalISel] Add detailed tests for lower callPetar Avramovic2019-05-312-5/+298
| | | | | | | | | | | | | | | | Test different operand types of callee and their behavior whether relocation model is pic or not. Possible operand types are: Register (function pointer), External symbol (used for libcalls e.g. __udivdi3 or memcpy), Global address. Global address has different handling depending on relocation model and linkage type. Register and external symbol do not. Differential Revision: https://reviews.llvm.org/D62590 llvm-svn: 362212
* Follow up and fix for rL362064Sjoerd Meijer2019-05-311-1/+2
| | | | | | | | Fix the misleadingly indentation introduced in rL362064. This will get rid of the compiler warning, and it was actually a bug. This change will be used and tested in D62669. llvm-svn: 362211
* [MIPS GlobalISel] Handle position independent code Petar Avramovic2019-05-319-19/+451
| | | | | | | | | | | | | Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
* [NFC][InstCombine] Copy add/sub constant-folding tests from codegenRoman Lebedev2019-05-311-0/+536
| | | | | | Last three patterns are missed. llvm-svn: 362209
* [NFC][Codegen] Add/sub constant-folding: add scalar tests tooRoman Lebedev2019-05-312-182/+953
| | | | | | Just for completeness. llvm-svn: 362208
* [ELF][test] Restore linkerscript/symbol-location.s to test ↵Fangrui Song2019-05-311-0/+16
| | | | | | | | | | | | getLinkerScriptLocation() The test (the only test that checks getLinkerScriptLocation()) deleted by r358652 can be restored by replacing R_X86_64_PLT32 with R_X86_64_PC32, and changing -pie to -shared (preemptable). Then, the symbol will not be a link-time constant and a -fPIC error will be issued. llvm-svn: 362207
* [mips] Move initGlobalBaseReg to MipsFunctionInfo. NFCPetar Avramovic2019-05-314-94/+93
| | | | | | | | | | | Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
* [InstructionSimplify] Add missing implementation of llvm::SimplifyUnOp. NFCCraig Topper2019-05-311-0/+4
| | | | | | | There are no callers currently, but the function is declared so we should at least implement it. llvm-svn: 362205
* [MIPS GlobalISel] Lower call for callee that is registerPetar Avramovic2019-05-312-6/+28
| | | | | | | | | Lower call for callee that is register for MIPS32. Register should contain callee function address. Differential Revision: https://reviews.llvm.org/D62585 llvm-svn: 362204
* [X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.Craig Topper2019-05-316-77/+36
| | | | | | | | | | | | | | These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits. Similar to PR42079. Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the load pattern used in the instructions. This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe we should use VZMOVL for widened loads even when we don't need the upper bits as zeroes? llvm-svn: 362203
* [X86] Add test cases for failure to use 128-bit masked vcvtdq2pd when load ↵Craig Topper2019-05-312-0/+212
| | | | | | starts as v2i32. llvm-svn: 362202
* [X86] Add test cases for a volatile load shrinking bug involving cvtdq2pd. NFCCraig Topper2019-05-312-276/+308
| | | | | | Similar to PR42079 llvm-svn: 362201
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