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* [Clang-tidy] Alphabetical sort of files/checks. Add space after clang-tidy ↵Eugene Zelenko2018-09-2011-20/+20
| | | | | | in source code headers. llvm-svn: 342601
* Thread safety analysis: Handle ObjCIvarRefExpr in SExprBuilder::translateAaron Puchert2018-09-193-3/+64
| | | | | | | | | | | | | | | | | Summary: This imitates the code for MemberExpr. Fixes PR38896. Reviewers: aaron.ballman, delesley, lukasza, rjmccall Reviewed By: delesley Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D52200 llvm-svn: 342600
* Revert "Implement LWG 2221 - No formatted output operator for nullptr."Volodymyr Sapsai2018-09-193-92/+3
| | | | | | | | | This reverts r342566 as it causes on bots linker errors like > Undefined symbols for architecture i386: > "std::__1::basic_ostream<char, std::__1::char_traits<char> >::operator<<(std::nullptr_t)", referenced from: llvm-svn: 342599
* [WEB] add new flags to a DebugInfo lit testMichael Berg2018-09-191-1/+1
| | | | llvm-svn: 342598
* [New PM] Introducing PassInstrumentation frameworkFedor Sergeev2018-09-1922-35/+720
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass Execution Instrumentation interface enables customizable instrumentation of pass execution, as per "RFC: Pass Execution Instrumentation interface" posted 06/07/2018 on llvm-dev@ The intent is to provide a common machinery to implement all the pass-execution-debugging features like print-before/after, opt-bisect, time-passes etc. Here we get a basic implementation consisting of: * PassInstrumentationCallbacks class that handles registration of callbacks and access to them. * PassInstrumentation class that handles instrumentation-point interfaces that call into PassInstrumentationCallbacks. * Callbacks accept StringRef which is just a name of the Pass right now. There were some ideas to pass an opaque wrapper for the pointer to pass instance, however it appears that pointer does not actually identify the instance (adaptors and managers might have the same address with the pass they govern). Hence it was decided to go simple for now and then later decide on what the proper mental model of identifying a "pass in a phase of pipeline" is. * Callbacks accept llvm::Any serving as a wrapper for const IRUnit*, to remove direct dependencies on different IRUnits (e.g. Analyses). * PassInstrumentationAnalysis analysis is explicitly requested from PassManager through usual AnalysisManager::getResult. All pass managers were updated to run that to get PassInstrumentation object for instrumentation calls. * Using tuples/index_sequence getAnalysisResult helper to extract generic AnalysisManager's extra args out of a generic PassManager's extra args. This is the only way I was able to explicitly run getResult for PassInstrumentationAnalysis out of a generic code like PassManager::run or RepeatedPass::run. TODO: Upon lengthy discussions we agreed to accept this as an initial implementation and then get rid of getAnalysisResult by improving RepeatedPass implementation. * PassBuilder takes PassInstrumentationCallbacks object to pass it further into PassInstrumentationAnalysis. Callbacks registration should be performed directly through PassInstrumentationCallbacks. * new-pm tests updated to account for PassInstrumentationAnalysis being run * Added PassInstrumentation tests to PassBuilderCallbacks unit tests. Other unit tests updated with registration of the now-required PassInstrumentationAnalysis. Reviewers: chandlerc, philip.pfaffe Differential Revision: https://reviews.llvm.org/D47858 llvm-svn: 342597
* Revert "[XRay][compiler-rt] FDRLogWriter Abstraction" and 1 more.Evgeniy Stepanov2018-09-199-317/+91
| | | | | | | | Revert the following 2 commits to fix standalone compiler-rt build: * r342523 [XRay] Detect terminfo library * r342518 [XRay][compiler-rt] FDRLogWriter Abstraction llvm-svn: 342596
* [x86] add test for 256-bit andn (PR37749); NFCSanjay Patel2018-09-191-0/+29
| | | | llvm-svn: 342595
* [SelectionDAG] allow vector types with isBitwiseNot()Sanjay Patel2018-09-194-12/+11
| | | | | | | The test diff in not-and-simplify.ll is from a use in SimplifyDemandedBits, and the test diff in add.ll is from a DAGCombiner transform. llvm-svn: 342594
* Fix the build when LLVM_TARGETS_TO_BUILD is empty.Juergen Ributzka2018-09-191-1/+0
| | | | | | | | | | | | | | | Using LLVMTestingSupport in the LLVM_LINK_COMPONENTS breaks the build when LLVM_TARGETS_TO_BUILD is set to empty. Libraries that depend on LLVMTestingSupport need to use target_link_libraries(<target> PRIVATE LLVMTestingSupport) instead. This required change was already commited by r341899 to fix another build issue. This fixes rdar://problem/44615064. llvm-svn: 342593
* [x86] add test for add+not vector fold; NFCSanjay Patel2018-09-191-0/+41
| | | | | | The fold uses 'isBitwiseNot()', but that's not vector-friendly currently. llvm-svn: 342592
* AArch64: Add FuseCryptoEOR fusion rulesMatthias Braun2018-09-194-0/+102
| | | | | | | | There's some additional rules available on newer apple CPUs. rdar://41235346 llvm-svn: 342590
* MachineScheduler: Add -misched-print-dags flagMatthias Braun2018-09-191-1/+6
| | | | | | | | Add a flag to dump the schedule DAG to the debug stream. This will be used in upcoming commits to test schedule DAG mutations such as macro fusion. llvm-svn: 342589
* Workaround a limitation of llvm::Any when used with types that haveChandler Carruth2018-09-191-0/+10
| | | | | | | | | a converting constructor from llvm::Any like gmock matchers. This issue has come up elsewhere as well and the workaround here is being considered for use in the standard long-term, but we can pretty cheaply experiment with it to see if anything ends up going wrong. llvm-svn: 342588
* [NFC] Declare instead of define non-void functions in unit tests.Shuai Wang2018-09-191-6/+6
| | | | llvm-svn: 342586
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-09-191-0/+6
| | | | | | Fine tune the cost model for all Exynos processors. llvm-svn: 342585
* [sanitizer][fuchsia] Fix VMAR leakKostya Kortchinsky2018-09-191-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Destroy and close a range's vmar if all its memory was unmapped. This addresses some performance regression due to the proliferation of vmars when Secondary backed allocations are concerned with Scudo on Fuchsia. When a Secondary backed allocation was freed, the associated `ReservedAddressRange` was going away after unmapping the entirety of the mapping, but without getting rid of the associated vmar properly (which was created specifically for that mapping). This resulted in an increase of defunct vmars, that in turn slowed down further new vmar allocations. This appears to solve ZX-2560/ZX-2642, at least on QEMU. Reviewers: flowerhack, mcgrathr, phosek, mseaborn Reviewed By: mcgrathr Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits Differential Revision: https://reviews.llvm.org/D52242 llvm-svn: 342584
* [ARM] Refactor Exynos feature set (NFC)Evandro Menezes2018-09-193-71/+23
| | | | | | | Since all Exynos processors share the same feature set, fold them in the implied fatures list for the subtarget. llvm-svn: 342583
* [InstCombine] Disable strcmp->memcmp transform for MSan.Matt Morehouse2018-09-192-1/+19
| | | | | | | | | | | | | | | | | | Summary: The strcmp->memcmp transform can make the resulting memcmp read uninitialized data, which MSan doesn't like. Resolves https://github.com/google/sanitizers/issues/993. Reviewers: eugenis, xbolva00 Reviewed By: eugenis Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D52272 llvm-svn: 342582
* test: actually fix the condition properlySaleem Abdulrasool2018-09-191-1/+1
| | | | | | | | I had locally changed the test to add an explicit triple to figure out the issue with the SCEI buildbots, and that hid the error. This now works with and without the explicit triple. llvm-svn: 342581
* [X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim2018-09-19223-10925/+11434
| | | | | | | | | | | | | | Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
* Copy utilities updated and added for MI flagsMichael Berg2018-09-197-3/+284
| | | | | | | | | | | | | | Summary: This patch adds a GlobalIsel copy utility into MI for flags and updates the instruction emitter for the SDAG path. Some tests show new behavior and I added one for GlobalIsel which mirrors an SDAG test for handling nsw/nuw. Reviewers: spatel, wristow, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D52006 llvm-svn: 342576
* [x86] change names of vector splitting helper functions; NFCSanjay Patel2018-09-191-16/+15
| | | | | | | | | | | As the code comments suggest, these are about splitting, and they are not necessarily limited to lowering, so that misled me. There's nothing that's actually x86-specific in these either, so they might be better placed in a common header so any target can use them. llvm-svn: 342575
* [ThinLTO] Write TYPE_IDs for types used in functions imported by aliasesVitaly Buka2018-09-193-6/+44
| | | | | | | | | | | | | | | | | | | | | | | Summary: ThinLTO imports alias as a copy of a aliasee, so when we import such functions with type tests we will need type ids used by function. However after D49565 we pick types only during processing of FunctionSummary which is not happening for such aliesees. Example: Unit U1 with a type, a functions F with the type check, and an alias A to the function. Unit U2 with only call to the alias A. In particular, this happens when we use -mconstructor-aliases, which is default. So if c++ unit only creates instance of the class, without calling any other methods it will lack of necessary type ids, which will result in false CFI reports. Reviewers: tejohnson, eugenis Subscribers: pcc, mehdi_amini, inglorion, eraman, hiraditya, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D52201 llvm-svn: 342574
* [ThinLTO] Extract getReferencedTypeIds from [NFC]Vitaly Buka2018-09-191-12/+33
| | | | | | | | | | | | Summary: Refactoring before D52201 Reviewers: eugenis, tejohnson Subscribers: pcc, inglorion, hiraditya, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D52203 llvm-svn: 342573
* [mips][microMIPS] Extending size reduction pass with MOVEPSimon Atanasyan2018-09-194-11/+224
| | | | | | | | | | | The patch extends size reduction pass for MicroMIPS. Two MOVE instructions are transformed into one MOVEP instrucition. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52037 llvm-svn: 342572
* [mips][microMIPS] Fix the definition of MOVEP instructionSimon Atanasyan2018-09-197-134/+117
| | | | | | | | | | | | The patch fixes definition of MOVEP instruction. Two registers are used instead of register pairs. This is necessary as machine verifier cannot handle register pairs. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52035 llvm-svn: 342571
* test: improve condition for the checkSaleem Abdulrasool2018-09-191-1/+1
| | | | | | | When the type of `wint_t` is `int`, the promotion will allow this to pass. Check this explicitly rather than using the size. llvm-svn: 342569
* redirecting to llvm.org/devmtgSylvestre Ledru2018-09-192-31/+4
| | | | llvm-svn: 342568
* [LLJIT] Add API to expose linking layer from LLJIT classesChris Bieneman2018-09-191-0/+3
| | | | | | | | | | | | Summary: This patch just surfaces the object linking layer from the LLJIT classes so that clients can take advantage of the changes implemented in r341154. Reviewers: lhames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51551 llvm-svn: 342567
* Implement LWG 2221 - No formatted output operator for nullptr. Reviewed as ↵Marshall Clow2018-09-193-3/+92
| | | | | | https://reviews.llvm.org/D44263 llvm-svn: 342566
* Sema: handle `wint_t` more carefully for printf checkingSaleem Abdulrasool2018-09-193-6/+11
| | | | | | | | | In the case that `win_t` is an `unsigned short` (e.g. on Windows), we would previously incorrectly diagnose the conversion because we would immediately promote the argument type from `wint_t` (aka `unsigned short`) to `int` before checking if the type matched. This should repair the Windows hosted bots. llvm-svn: 342565
* [X86] Add initial SimplifyDemandedVectorEltsForTargetNode supportSimon Pilgrim2018-09-1919-395/+439
| | | | | | | | | | | | | | This patch adds an initial x86 SimplifyDemandedVectorEltsForTargetNode implementation to handle target shuffles. Currently the patch only decodes a target shuffle, calls SimplifyDemandedVectorElts on its input operands and removes any shuffle that reduces to undef/zero/identity. Future work will need to integrate this with combineX86ShufflesRecursively, add support for other x86 ops, etc. NOTE: There is a minor regression that appears to be affecting further (extractelement?) combines which I haven't been able to solve yet - possibly something to do with how nodes are added to the worklist after simplification. Differential Revision: https://reviews.llvm.org/D52140 llvm-svn: 342564
* [DataFormatters] Add formatter for C++17 std::variantShafik Yaghmour2018-09-199-0/+458
| | | | | | | | | | rdar://problem/43691454 Patch by Shafik Yaghmour. Differential Revision: https://reviews.llvm.org/D51520 llvm-svn: 342563
* [analyzer] Fix nullptr access when processing instantiated function in ↵Shuai Wang2018-09-192-1/+31
| | | | | | ExprMutationAnalyzer. llvm-svn: 342562
* Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555.Andrea Di Biagio2018-09-191-1/+1
| | | | | | | | | | | | | | | | | | The reason why build #25777 might have failed is because the SmallVector move constructor is _not_ noexcept, and the stl implementation used by that buildbot calls _VSTD::move_if_noexcept() (according to the backtrace). OpcodeInfo has a default move constructor, and the copy constructor is deleted. However, as far as I can see, SmallVector doesn't declare a noexcept move constructor. So, what I believe it is happening here is that, _VSTD::move_if_noexcept() returns an lvalue reference and not an rvalue reference. This eventually triggers a copy that fails to compile. Hopefully, using a std::vector instead of SmallVector (as it was originally suggested by Simon in the code review) should be enough to unbreak the buildbot. llvm-svn: 342561
* Don't require relops on variant alternatives to all return the sameEric Fiselier2018-09-193-35/+182
| | | | | | | | | | | | type. Libc++ correctly asserts that a set of visitors for a variant all return the same type. However, we use the visitation machinary to perform relational operations. This causes a static assertion when some of the alternatives relops return a UDT which is implicitly convertible to bool instead of 'bool' exactly. llvm-svn: 342560
* [AMDGPU] Add instruction selection for i1 to f16 conversionCarl Ritson2018-09-193-0/+48
| | | | | | | | | | | | | | | | | | Summary: This is required for GPUs with 16 bit instructions where f16 is a legal register type and hence int_to_fp i1 to f16 is not lowered by legalizing. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52018 Change-Id: Ie4c0fd6ced7cf10ad612023c6879724d9ded5851 llvm-svn: 342558
* Basic: correct `__WINT_TYPE__` on WindowsSaleem Abdulrasool2018-09-194-6/+8
| | | | | | | | | Windows uses `unsigned short` for `wint_t`. Correct the type definition as vended by the compiler. This type is defined in corecrt.h and is unconditionally typedef'ed. cl does not have an equivalent to `__WINT_TYPE__` which is why this was never detected. llvm-svn: 342557
* [bpf] Symbol sizes and types in object fileYonghong Song2018-09-191-2/+2
| | | | | | | | | | | | Clang-compiled object files currently don't include the symbol sizes and types. Some tools however need that information. For example, ctfconvert uses that information to generate FreeBSD's CTF representation from ELF files. With this patch, symbol sizes and types are included in object files. Signed-off-by: Paul Chaignon <paul.chaignon@orange.com> Reported-by: Yutaro Hayakawa <yhayakawa3720@gmail.com> llvm-svn: 342556
* [TableGen][SubtargetEmitter] Add the ability for processor models to ↵Andrea Di Biagio2018-09-1913-92/+1164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | describe dependency breaking instructions. This patch adds the ability for processor models to describe dependency breaking instructions. Different processors may specify a different set of dependency-breaking instructions. That means, we cannot assume that all processors of the same target would use the same rules to classify dependency breaking instructions. The main goal of this patch is to provide the means to describe dependency breaking instructions directly via tablegen, and have the following TargetSubtargetInfo hooks redefined in overrides by tabegen'd XXXGenSubtargetInfo classes (here, XXX is a Target name). ``` virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const { return false; } virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const { return isZeroIdiom(MI); } ``` An instruction MI is a dependency-breaking instruction if a call to method isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to true. Similarly, an instruction MI is a special case of zero-idiom dependency breaking instruction if a call to STI.isZeroIdiom(MI) returns true. The extra APInt is used for those targets that may want to select which machine operands have their dependency broken (see comments in code). Note that by default, subtargets don't know about the existence of dependency-breaking. In the absence of external information, those method calls would always return false. A new tablegen class named STIPredicate has been added by this patch to let processor models classify instructions that have properties in common. The idea is that, a MCInstrPredicate definition can be used to "generate" an instruction equivalence class, with the idea that instructions of a same class all have a property in common. STIPredicate definitions are essentially a collection of instruction equivalence classes. Also, different processor models can specify a different variant of the same STIPredicate with different rules (i.e. predicates) to classify instructions. Tablegen backends (in this particular case, the SubtargetEmitter) will be able to process STIPredicate definitions, and automatically generate functions in XXXGenSubtargetInfo. This patch introduces two special kind of STIPredicate classes named IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a definition for those in the BtVer2 scheduling model only. This patch supersedes the one committed at r338372 (phabricator review: D49310). The main advantages are: - We can describe subtarget predicates via tablegen using STIPredicates. - We can describe zero-idioms / dep-breaking instructions directly via tablegen in the scheduling models. In future, the STIPredicates framework can be used for solving other problems. Examples of future developments are: - Teach how to identify optimizable register-register moves - Teach how to identify slow LEA instructions (each subtarget defining its own concept of "slow" LEA). - Teach how to identify instructions that have undocumented false dependencies on the output registers on some processors only. It is also (in my opinion) an elegant way to expose knowledge to both external tools like llvm-mca, and codegen passes. For example, machine schedulers in LLVM could reuse that information when internally constructing the data dependency graph for a code region. This new design feature is also an "opt-in" feature. Processor models don't have to use the new STIPredicates. It has all been designed to be as unintrusive as possible. Differential Revision: https://reviews.llvm.org/D52174 llvm-svn: 342555
* [DAGCombiner][x86] add transform/hook to decompose integer multiply into ↵Sanjay Patel2018-09-1913-497/+351
| | | | | | | | | | | | | | | | | | | | | shift/add This is an alternative to D37896. I don't see a way to decompose multiplies generically without a target hook to tell us when it's profitable. ARM and AArch64 may be able to remove some duplicate code that overlaps with this transform. As a first step, we're only getting the most clear wins on the vector examples requested in PR34474: https://bugs.llvm.org/show_bug.cgi?id=34474 As noted in the code comment, it's likely that the x86 constraints are tighter than necessary, but it may not always be a win to replace a pmullw/pmulld. Differential Revision: https://reviews.llvm.org/D52195 llvm-svn: 342554
* [UBSan] Fix typo in CMake conditional that checked if the architectureDan Liew2018-09-191-1/+1
| | | | | | | | | | | | | | of a darwin platform was in the list of `UBSAN_SUPPORTED_ARCH`. This is a follow up to r341306. The typo meant that if an architecture was a prefix to another architecture in the list (e.g. `armv7` is a prefix of `armv7k`) then this would trigger a match which is not the intended behaviour. rdar://problem/41126835 llvm-svn: 342553
* Revert rL342544: [New PM] Introducing PassInstrumentation frameworkFedor Sergeev2018-09-1922-720/+35
| | | | | | A bunch of bots fail to compile unittests. Reverting. llvm-svn: 342552
* Fix -Wsign-compare warnings. NFCISimon Pilgrim2018-09-191-10/+10
| | | | llvm-svn: 342551
* [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IRAlex Bradbury2018-09-198-29/+66
| | | | | | | | | | | | | | | | | This involves changing the shouldExpandAtomicCmpXchgInIR interface, but I have updated the in-tree backends using this hook (ARM, AArch64, Hexagon) so they will see no functional change. Previously this hook returned bool, but it now returns AtomicExpansionKind. This hook allows targets to select how a given cmpxchg is to be expanded. D48131 uses this to expand part-word cmpxchg to a target-specific intrinsic. See my associated RFC for more info on the motivation for this change <http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html>. Differential Revision: https://reviews.llvm.org/D48130 llvm-svn: 342550
* [benchmark] Cherrypick fix for MinGW/ARM from upstreamMartin Storsjo2018-09-193-1/+6
| | | | | | | | | | This fixes building for Windows on ARM, with MinGW headers. (Building for Windows on ARM with Windows SDK still is unsupported by the benchmark library.) Differential Revision: https://reviews.llvm.org/D52262 llvm-svn: 342549
* [InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanonical ((-1 << y) ↵Roman Lebedev2018-09-193-55/+43
| | | | | | | | | | | | | | | | | | | | | | >> y) mask Summary: The last low-bit-mask-pattern-producing-pattern i can think of. https://rise4fun.com/Alive/UGzE <- non-canonical But we can not canonicalize it because of extra uses. https://bugs.llvm.org/show_bug.cgi?id=38123 Reviewers: spatel, craig.topper, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52148 llvm-svn: 342548
* [InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanonical ((1 << ↵Roman Lebedev2018-09-193-80/+65
| | | | | | | | | | | | | | | | | | | y)+(-1)) mask Summary: Same as to D52146. `((1 << y)+(-1))` is simply non-canoniacal version of `~(-1 << y)`: https://rise4fun.com/Alive/0vl We can not canonicalize it due to the extra uses. But we can handle it here. Reviewers: spatel, craig.topper, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52147 llvm-svn: 342547
* [InstCombine] foldICmpWithLowBitMaskedVal(): handle ~(-1 << y) maskRoman Lebedev2018-09-193-114/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Two folds are happening here: 1. https://rise4fun.com/Alive/oaFX 2. And then `foldICmpWithHighBitMask()` (D52001): https://rise4fun.com/Alive/wsP4 This change doesn't just add the handling for eq/ne predicates, it actually builds upon the previous `foldICmpWithLowBitMaskedVal()` work, so **all** the 16 fold variants* are immediately supported. I'm indeed only testing these two predicates. I do not feel like re-proving all 16 folds*, because they were already proven for the general case of constant with all-ones in low bits. So as long as the mask produces all-ones in low bits, i'm pretty sure the fold is valid. But required, i can re-prove, let me know. * eq/ne are commutative - 4 folds; ult/ule/ugt/uge - are not commutative (the commuted variant is InstSimplified), 4 folds; slt/sle/sgt/sge are not commutative - 4 folds. 12 folds in total. https://bugs.llvm.org/show_bug.cgi?id=38123 https://bugs.llvm.org/show_bug.cgi?id=38708 Reviewers: spatel, craig.topper, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52146 llvm-svn: 342546
* [ARM] Fix unwind information for floating point registersOliver Stannard2018-09-192-3/+22
| | | | | | | | | | | | Fixes the unwind information generated for floating-point registers. Previously, all padding registers were assumed to be four bytes wide. Now, the width of the register is used to specify the amount of padding. Patch by Jackson Woodruff! Differential revision: https://reviews.llvm.org/D51494 llvm-svn: 342545
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