summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-3043-322/+2133
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* clang-cl: Expose -fmerge-all-constantsHans Wennborg2018-04-302-1/+2
| | | | | | | Now that constant merging is off by default, we'd like a way to enable it on Windows. llvm-svn: 331214
* [MIR] Reset unique MBB numbering in MachineFunction::reset()Roman Tereshin2018-04-302-2/+8
| | | | | | | | | | | | | | No need to waste space nor number MBBs differently if MF gets recreated. Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar Reviewed By: qcolombet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46078 llvm-svn: 331213
* [OpenMP][OMPT] Fix api_calls_from_other_thread.cppJonathan Peyton2018-04-301-3/+3
| | | | | | | Removed environment setting in RUN: line that was being ignored anyways. Changed a few specific checks to "any number" llvm-svn: 331212
* [OPENMP] Do not emit warning about non-declared target function params.Alexey Bataev2018-04-302-4/+4
| | | | | | | | We should not emit warning that the parameters are not marked as declare target, these declaration are local and cannot be marked as declare target. llvm-svn: 331211
* [DAGCombiner] rename function attribute for disabling ftrunc transformSanjay Patel2018-04-303-8/+7
| | | | | | | | | | This is the matching name change for the Clang patch at: D46236 rL331209 Differential Revision: https://reviews.llvm.org/D46237 llvm-svn: 331210
* [Driver, CodeGen] rename options to disable an FP cast optimizationSanjay Patel2018-04-309-43/+49
| | | | | | | | | | | | | | As suggested in the post-commit thread for rL331056, we should match these clang options with the established vocabulary of the corresponding sanitizer option. Also, the use of 'strict' is well-known for these kinds of knobs, and we can improve the descriptive text in the docs. So this intends to match the logic of D46135 but only change the words. Matching LLVM commit to match this spelling of the attribute to follow shortly. Differential Revision: https://reviews.llvm.org/D46236 llvm-svn: 331209
* [X86] Introduce X86SchedWriteWidths schedule wrapper for different vector ↵Simon Pilgrim2018-04-303-93/+160
| | | | | | | | | | | | | | widths. We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required. I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future. This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality. Differential Revision: https://reviews.llvm.org/D46266 llvm-svn: 331208
* Regenerated AST Matchers doc.Alexander Kornienko2018-04-302-7/+9
| | | | | | Backported a minor fix to the comment in the header. llvm-svn: 331207
* [OPENMP] Do not crash on codegen for CXX member functions.Alexey Bataev2018-04-302-0/+9
| | | | | | | Non-static member functions should not be emitted as a standalone functions, this leads to compiler crash. llvm-svn: 331206
* [InstCombine] Unfold masked merge with constant maskRoman Lebedev2018-04-303-70/+80
| | | | | | | | | | | | | | | | | Summary: As discussed in D45733, we want to do this in InstCombine. https://rise4fun.com/Alive/LGk Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: chandlerc, xbolva00, llvm-commits Differential Revision: https://reviews.llvm.org/D45867 llvm-svn: 331205
* [InstCombine][NFC] Add tests for unfolding masked merge with constant maskRoman Lebedev2018-04-302-0/+643
| | | | | | | | Summary: As discussed in D45733, we want to do this in InstCombine. Differential Revision: https://reviews.llvm.org/D45866 llvm-svn: 331204
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-3051-79/+11018
| | | | | | | | | | | | | | | | This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-3015-249/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
* Fix infinite loop after r331115Daniel Sanders2018-04-303-1/+67
| | | | | | | | There are two separate fixes here: * The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction. * The target should not be requesting lowering of non-extending loads. llvm-svn: 331201
* [DebugInfo] Prevent infinite recursion for malformed DWARFJonas Devlieghere2018-04-302-10/+326
| | | | | | | | | | | This prevents infinite recursion in DWARFDie::findRecursively for malformed DWARF where a DIE references itself. This fixes PR36257. Differential revision: https://reviews.llvm.org/D43092 llvm-svn: 331200
* [SLPVectorizer] Debug info shouldn't impact spill cost computation.Davide Italiano2018-04-302-1/+97
| | | | | | | | | | <rdar://problem/39794738> (Also, PR32761). Differential Revision: https://reviews.llvm.org/D46199 llvm-svn: 331199
* [X86][Atom] Remove unnecessary x87 load/move instrw overrides.Simon Pilgrim2018-04-301-3/+2
| | | | llvm-svn: 331198
* Reflow paragraphs in comments.Adrian Prantl2018-04-30604-13438/+11190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is intended as a clean up after the big clang-format commit (r280751), which unfortunately resulted in many of the comment paragraphs in LLDB being very hard to read. FYI, the script I used was: import textwrap import commands import os import sys import re tmp = "%s.tmp"%sys.argv[1] out = open(tmp, "w+") with open(sys.argv[1], "r") as f: header = "" text = "" comment = re.compile(r'^( *//) ([^ ].*)$') special = re.compile(r'^((([A-Z]+[: ])|([0-9]+ )).*)|(.*;)$') for line in f: match = comment.match(line) if match and not special.match(match.group(2)): # skip intentionally short comments. if not text and len(match.group(2)) < 40: out.write(line) continue if text: text += " " + match.group(2) else: header = match.group(1) text = match.group(2) continue if text: filled = textwrap.wrap(text, width=(78-len(header)), break_long_words=False) for l in filled: out.write(header+" "+l+'\n') text = "" out.write(line) os.rename(tmp, sys.argv[1]) Differential Revision: https://reviews.llvm.org/D46144 llvm-svn: 331197
* AMDGPU: Remove some dead codeTom Stellard2018-04-301-4/+0
| | | | llvm-svn: 331196
* [OPENMP] Do not crash on incorrect input data.Alexey Bataev2018-04-303-12/+63
| | | | | | | | Emit error messages instead of compiler crashing when the target region does not exist in the device code + fix crash when the location comes from macros. llvm-svn: 331195
* Match also DW_TAG_partial_unit when DW_TAG_compile_unit is matchedJan Kratochvil2018-04-309-19/+42
| | | | | | | | | | Code commonly checks if the parent DIE is DW_TAG_compile_unit. But DW_TAG_partial_unit also acts as DW_TAG_compile_unit for DWZ as DWZ is using DW_TAG_imported_unit only at the top unit level. Differential revision: https://reviews.llvm.org/D40469 llvm-svn: 331194
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-303-2/+48
| | | | | | | | | | | | | | | | This fixes PR37293. We can have scheduling classes with no write latency entries, that still consume processor resources. We don't want to treat those instructions as zero-latency instructions; they still have to be issued to the underlying pipelines, so they still consume resource cycles. This is likely to be a regression which I have accidentally introduced at revision 330807. Now, if an instruction has a non-empty set of write processor resources, we conservatively treat it as a normal (i.e. non zero-latency) instruction. llvm-svn: 331193
* [SystemZ] Refactor some VT casts in DAG match patternsUlrich Weigand2018-04-301-59/+59
| | | | | | | | | | | | | | In patterns where we need to specify a result VT, prefer [(set (tr.vt tr.op:$V1), (operator ...))] over [(set tr.op:$V1, (tr.vt (operator ...)))] This is NFC now, but simplifies some future changes. llvm-svn: 331192
* [SystemZ] Improve handling of Select pseudo-instructionsUlrich Weigand2018-04-307-32/+32
| | | | | | | | | | | | | | | If we have LOCR instructions, select them directly from SelectionDAG instead of first going through a pseudo instruction and then using the custom inserter to emit the LOCR. Provide Select pseudo-instructions for VR32/VR64 if we have vector instructions, to avoid having to go through the first 16 FPRs unnecessarily. If we do not have LOCFHR, prefer using LOCR followed by a move over a conditional branch. llvm-svn: 331191
* IWYU for llvm-config.h, removals. Also see r331184.Nico Weber2018-04-305-5/+0
| | | | llvm-svn: 331190
* [clangd] Using index for GoToDefinition.Haojian Wu2018-04-306-85/+275
| | | | | | | | | | | | | | | | | | | Summary: This patch adds index support for GoToDefinition -- when we don't get the definition from local AST, we query our index (Static&Dynamic) index to get it. Since we currently collect top-level symbol in the index, it doesn't support all cases (e.g. class members), we will extend the index to include more symbols in the future. Reviewers: sammccall Subscribers: klimek, ilya-biryukov, jkorous-apple, ioeric, MaskRay, cfe-commits Differential Revision: https://reviews.llvm.org/D45717 llvm-svn: 331189
* [X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.Simon Pilgrim2018-04-301-1/+0
| | | | llvm-svn: 331188
* [X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.Simon Pilgrim2018-04-301-1/+1
| | | | llvm-svn: 331187
* AMDGPU/GlobalISel: Don't try to lower geometry shadersTom Stellard2018-04-301-0/+3
| | | | | | | | | | | | | | Summary: The AMDGPU_GS calling convention is not supported yet. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46041 llvm-svn: 331186
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-30152-15/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See r331124 for how I made a list of files missing the include. I then ran this Python script: for f in open('filelist.txt'): f = f.strip() fl = open(f).readlines() found = False for i in xrange(len(fl)): p = '#include "llvm/' if not fl[i].startswith(p): continue if fl[i][len(p):] > 'Config': fl.insert(i, '#include "llvm/Config/llvm-config.h"\n') found = True break if not found: print 'not found', f else: open(f, 'w').write(''.join(fl)) and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p` and tried to fix include ordering and whatnot. No intended behavior change. llvm-svn: 331184
* [BranchFolding] Salvage DBG_VALUE instructions from empty blocksBjorn Pettersson2018-04-302-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch will introduce copying of DBG_VALUE instructions from an otherwise empty basic block to predecessor/successor blocks in case the empty block is eliminated/bypassed. It is currently only done in one identified situation in the BranchFolding pass, before optimizing on empty block. It can be seen as a light variant of the propagation done by the LiveDebugValues pass, which unfortunately is executed after the BranchFolding pass. We only propagate (copy) DBG_VALUE instructions in a limited number of situations: a) If the empty BB is the only predecessor of a successor we can copy the DBG_VALUE instruction to the beginning of the successor (because the DBG_VALUE instruction is always part of the flow between the blocks). b) If the empty BB is the only successor of a predecessor we can copy the DBG_VALUE instruction to the end of the predecessor (because the DBG_VALUE instruction is always part of the flow between the blocks). In this case we add the DBG_VALUE just before the first terminator (assuming that the terminators do not impact the DBG_VALUE). A future solution, to handle more situations, could perhaps be to run the LiveDebugValues pass before branch folding? This fix is related to PR37234. It is expected to resolve the problem seen, when applied together with the fix in SelectionDAG from here: https://reviews.llvm.org/D46129 Reviewers: #debug-info, aprantl, rnk Reviewed By: #debug-info, aprantl Subscribers: ormris, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46184 llvm-svn: 331183
* [SelectionDAG] Improve selection of DBG_VALUE using a PHI node resultBjorn Pettersson2018-04-308-4/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When building the selection DAG at ISel all PHI nodes are selected and lowered to Machine Instruction PHI nodes before we start to create any SDNodes. So there are no SDNodes for values produced by the PHI nodes. In the past when selecting a dbg.value intrinsic that uses the value produced by a PHI node we have been handling such dbg.value intrinsics as "dangling debug info". I.e. we have not created a SDDbgValue node directly, because there is no existing SDNode for the PHI result, instead we deferred the creationg of a SDDbgValue until we found the first use of the PHI result. The old solution had a couple of flaws. The position of the selected DBG_VALUE instruction would end up quite late in a basic block, and for example not directly after the PHI node as in the LLVM IR input. And in case there were no use at all in the basic block the dbg.value could be dropped completely. This patch introduces a new VREG kind of SDDbgValue nodes. It is similar to a SDNODE kind of node, but it refers directly to a virtual register and not a SDNode. When we do selection for a dbg.value that is using the result of a PHI node we can do a lookup of the virtual register directly (as it already is determined for the PHI node) and create a SDDbgValue node immediately instead of delaying the selection until we find a use. This should fix a problem with losing debug info at ISel as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234). It does not resolve PR37234 completely, because the debug info is dropped later on in the BranchFolder (see D46184). Reviewers: #debug-info, aprantl Reviewed By: #debug-info, aprantl Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46129 llvm-svn: 331182
* Fix warning: result of 32-bit shift implicitly converted to 64 bits - NFCZaara Syeda2018-04-301-1/+1
| | | | | | | | Fix warning caused by rL331046. Differential Revision: https://reviews.llvm.org/D45729 llvm-svn: 331181
* llgs tests: Use noack-mode for communication to avoid pr37294Pavel Labath2018-04-302-2/+16
| | | | llvm-svn: 331180
* NFC, Avoid a warning on pointer casting in PassPlugin.cppGabor Buella2018-04-301-2/+4
| | | | llvm-svn: 331179
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-304-69/+51
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* IWYU for llvm-config.h in clang. See r331124 for details.Nico Weber2018-04-3013-8/+5
| | | | llvm-svn: 331177
* Remove unnecessary indirection. No behavior change.Nico Weber2018-04-301-12/+6
| | | | llvm-svn: 331176
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-304-51/+69
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-8/+3
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D46254 llvm-svn: 331174
* ObjectFileELF: Add support for arbitrarily named code sectionsPavel Labath2018-04-305-0/+73
| | | | | | | | | | | | | | | | | | | ObjectFileELF assumes that code section has ".text" name. There is an exception for kalimba toolchain that can use arbitrary names, but other toolchains also could use arbitrary names for code sections. For example, corert uses separate section for compiled managed code. As lldb doesn't recognize such section it leads to problem with breakpoints on arm, because debugger cannot determine instruction set (arm/thumb) and uses incorrect breakpoint opcode that breaks program execution. This change allows debugger to correctly handle such code sections. We assume that section is a code section if it has SHF_EXECINSTR flag set and has SHT_PROGBITS type. Patch by Konstantin Baladurin <k.baladurin@partner.samsung.com>. Differential Revision: https://reviews.llvm.org/D44998 llvm-svn: 331173
* Fixup r331049 (FileSpec auto-normalization)Pavel Labath2018-04-302-11/+5
| | | | | | | | | | | | | | | | | | A typo in the patch (using syntax instead of m_syntax) resulted in the normalization not working properly for windows filespecs when the syntax was passed as host-native. This did not affect the unit tests, as all of those pass an explicity syntax, but failed gloriously when running the full test suite. I also fix an expectation in an lldb-mi test, which was now failing because it was expecting a path to be echoed verbatim, but we were now normalizing it. As a drive-by, this also fixes the default-in-fully-covered-switch warning and removes an unused argument from the NeedsNormalization function. llvm-svn: 331172
* [bindings] Fix dibuilder go bindings after r331114.Benjamin Kramer2018-04-301-7/+7
| | | | llvm-svn: 331171
* [llvm-mca] Regenerate test Atom/resources-sse3.s. NFCAndrea Di Biagio2018-04-301-47/+41
| | | | | | Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom. llvm-svn: 331170
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-308-1/+3788
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [clangd] Also use UTF-16 in index position.Haojian Wu2018-04-302-7/+12
| | | | | | | | | | Reviewers: sammccall Subscribers: klimek, ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits Differential Revision: https://reviews.llvm.org/D46258 llvm-svn: 331168
* [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructionsSimon Pilgrim2018-04-301-20/+20
| | | | | | The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions. llvm-svn: 331167
* NFC - Typo fixes lib/VMCore -> lib/IRGabor Buella2018-04-302-2/+2
| | | | llvm-svn: 331166
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-306-41/+1565
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
OpenPOWER on IntegriCloud