diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/shift.ll | 4 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vec_sext.ll | 4 |
3 files changed, 6 insertions, 7 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 3108142397f..6c8eea1f1bc 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3153,9 +3153,10 @@ Instruction *InstCombiner::foldICmpUsingKnownBits(ICmpInst &I) { // If this is a normal comparison, it demands all bits. If it is a sign bit // comparison, it only demands the sign bit. bool IsSignBit = false; - if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { + const APInt *CmpC; + if (match(Op1, m_APInt(CmpC))) { bool UnusedBit; - IsSignBit = isSignBitCheck(Pred, CI->getValue(), UnusedBit); + IsSignBit = isSignBitCheck(Pred, *CmpC, UnusedBit); } APInt Op0KnownZero(BitWidth, 0), Op0KnownOne(BitWidth, 0); diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll index 12ab3535d4a..dab212dc583 100644 --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -628,11 +628,9 @@ define i1 @test35(i32 %X) { ret i1 %tmp2 } -; FIXME: Vectors should fold the same way. define <2 x i1> @test35vec(<2 x i32> %X) { ; CHECK-LABEL: @test35vec( -; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> %X, <i32 7, i32 7> -; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7> diff --git a/llvm/test/Transforms/InstCombine/vec_sext.ll b/llvm/test/Transforms/InstCombine/vec_sext.ll index be808e902ab..10947c1781e 100644 --- a/llvm/test/Transforms/InstCombine/vec_sext.ll +++ b/llvm/test/Transforms/InstCombine/vec_sext.ll @@ -3,8 +3,8 @@ define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: @psignd_3( -; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a +; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> ; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1> ; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> %a, [[T1]] ; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT]], [[SUB]] @@ -25,8 +25,8 @@ define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a +; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> ; CHECK-NEXT: [[B_LOBIT_NOT:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1> ; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT]], %a ; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT_NOT]], [[SUB]] |
