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-rw-r--r--llvm/include/llvm/CodeGen/MachineInstr.h8
-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.cpp2
-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.h2
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp6
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp4
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp4
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp4
-rw-r--r--llvm/lib/Target/SystemZ/SystemZElimCompare.cpp6
-rw-r--r--llvm/test/CodeGen/X86/fast-isel-select-sse.ll132
-rw-r--r--llvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll2
-rw-r--r--llvm/test/CodeGen/X86/fp-intrinsics-flags.ll20
-rw-r--r--llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll34
-rw-r--r--llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll12
13 files changed, 130 insertions, 106 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index a60244528df..6d4ab3b2a2a 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -104,8 +104,8 @@ public:
// no signed wrap.
IsExact = 1 << 13, // Instruction supports division is
// known to be exact.
- FPExcept = 1 << 14, // Instruction may raise floating-point
- // exceptions.
+ NoFPExcept = 1 << 14, // Instruction does not raise
+ // floatint-point exceptions.
};
private:
@@ -885,10 +885,10 @@ public:
/// instruction that can in principle raise an exception, as indicated
/// by the MCID::MayRaiseFPException property, *and* at the same time,
/// the instruction is used in a context where we expect floating-point
- /// exceptions might be enabled, as indicated by the FPExcept MI flag.
+ /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
bool mayRaiseFPException() const {
return hasProperty(MCID::MayRaiseFPException) &&
- getFlag(MachineInstr::MIFlag::FPExcept);
+ !getFlag(MachineInstr::MIFlag::NoFPExcept);
}
//===--------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 0c35a91f828..5976f5da156 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -204,7 +204,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("nuw" , MIToken::kw_nuw)
.Case("nsw" , MIToken::kw_nsw)
.Case("exact" , MIToken::kw_exact)
- .Case("fpexcept", MIToken::kw_fpexcept)
+ .Case("nofpexcept", MIToken::kw_nofpexcept)
.Case("debug-location", MIToken::kw_debug_location)
.Case("same_value", MIToken::kw_cfi_same_value)
.Case("offset", MIToken::kw_cfi_offset)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index af5327cacfe..aaffe4a4c91 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -73,7 +73,7 @@ struct MIToken {
kw_nuw,
kw_nsw,
kw_exact,
- kw_fpexcept,
+ kw_nofpexcept,
kw_debug_location,
kw_cfi_same_value,
kw_cfi_offset,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 11cab488e22..fbb834c4ceb 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1185,7 +1185,7 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Token.is(MIToken::kw_nuw) ||
Token.is(MIToken::kw_nsw) ||
Token.is(MIToken::kw_exact) ||
- Token.is(MIToken::kw_fpexcept)) {
+ Token.is(MIToken::kw_nofpexcept)) {
// Mine frame and fast math flags
if (Token.is(MIToken::kw_frame_setup))
Flags |= MachineInstr::FrameSetup;
@@ -1211,8 +1211,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Flags |= MachineInstr::NoSWrap;
if (Token.is(MIToken::kw_exact))
Flags |= MachineInstr::IsExact;
- if (Token.is(MIToken::kw_fpexcept))
- Flags |= MachineInstr::FPExcept;
+ if (Token.is(MIToken::kw_nofpexcept))
+ Flags |= MachineInstr::NoFPExcept;
lex();
}
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 1d61fdbba4d..e8cd3d60ccb 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -752,8 +752,8 @@ void MIPrinter::print(const MachineInstr &MI) {
OS << "nsw ";
if (MI.getFlag(MachineInstr::IsExact))
OS << "exact ";
- if (MI.getFlag(MachineInstr::FPExcept))
- OS << "fpexcept ";
+ if (MI.getFlag(MachineInstr::NoFPExcept))
+ OS << "nofpexcept ";
OS << TII->getName(MI.getOpcode());
if (I < E)
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index d3803b31f5c..c8e3e5bb01a 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1538,8 +1538,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << "nsw ";
if (getFlag(MachineInstr::IsExact))
OS << "exact ";
- if (getFlag(MachineInstr::FPExcept))
- OS << "fpexcept ";
+ if (getFlag(MachineInstr::NoFPExcept))
+ OS << "nofpexcept ";
// Print the opcode name.
if (TII)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index a0c8e83cd8a..c613c254062 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -882,8 +882,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
if (Flags.hasExact())
MI->setFlag(MachineInstr::MIFlag::IsExact);
- if (MI->getDesc().mayRaiseFPException() && !Flags.hasNoFPExcept())
- MI->setFlag(MachineInstr::MIFlag::FPExcept);
+ if (Flags.hasNoFPExcept())
+ MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
}
// Emit all of the actual operands of this instruction, adding them to the
diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
index 9e6d99f4305..2f0cf031702 100644
--- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -297,10 +297,10 @@ bool SystemZElimCompare::convertToLoadAndTest(
MIB.setMemRefs(MI.memoperands());
MI.eraseFromParent();
- // Mark instruction as raising an FP exception if applicable. We already
+ // Mark instruction as not raising an FP exception if applicable. We already
// verified earlier that this move is valid.
- if (Compare.mayRaiseFPException())
- MIB.setMIFlag(MachineInstr::MIFlag::FPExcept);
+ if (!Compare.mayRaiseFPException())
+ MIB.setMIFlag(MachineInstr::MIFlag::NoFPExcept);
return true;
}
diff --git a/llvm/test/CodeGen/X86/fast-isel-select-sse.ll b/llvm/test/CodeGen/X86/fast-isel-select-sse.ll
index 54ef4fdc114..17d2803e9ce 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select-sse.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select-sse.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -O0 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx512f | FileCheck %s --check-prefix=AVX512
@@ -12,9 +12,10 @@ define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_oeq_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpeqss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_oeq_f32:
@@ -38,9 +39,10 @@ define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_oeq_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpeqsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_oeq_f64:
@@ -64,9 +66,10 @@ define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ogt_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpltss %xmm0, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andnps %xmm3, %xmm1
-; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: orps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -91,10 +94,11 @@ define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ogt_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpltsd %xmm0, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm2, %xmm0
; SSE-NEXT: andnpd %xmm3, %xmm1
-; SSE-NEXT: orpd %xmm2, %xmm1
-; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: orpd %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ogt_f64:
@@ -118,9 +122,10 @@ define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_oge_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpless %xmm0, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andnps %xmm3, %xmm1
-; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: orps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -145,10 +150,11 @@ define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_oge_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmplesd %xmm0, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm2, %xmm0
; SSE-NEXT: andnpd %xmm3, %xmm1
-; SSE-NEXT: orpd %xmm2, %xmm1
-; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: orpd %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_oge_f64:
@@ -172,9 +178,10 @@ define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_olt_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpltss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_olt_f32:
@@ -198,9 +205,10 @@ define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_olt_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpltsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_olt_f64:
@@ -224,9 +232,10 @@ define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ole_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpless %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ole_f32:
@@ -250,9 +259,10 @@ define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ole_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmplesd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ole_f64:
@@ -276,9 +286,10 @@ define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ord_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpordss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ord_f32:
@@ -302,9 +313,10 @@ define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ord_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpordsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ord_f64:
@@ -328,9 +340,10 @@ define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_uno_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpunordss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_uno_f32:
@@ -354,9 +367,10 @@ define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_uno_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpunordsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_uno_f64:
@@ -380,9 +394,10 @@ define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ugt_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpnless %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ugt_f32:
@@ -406,9 +421,10 @@ define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ugt_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpnlesd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ugt_f64:
@@ -432,9 +448,10 @@ define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_uge_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpnltss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_uge_f32:
@@ -458,9 +475,10 @@ define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_uge_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpnltsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_uge_f64:
@@ -484,9 +502,10 @@ define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ult_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpnless %xmm0, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andnps %xmm3, %xmm1
-; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: orps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -511,10 +530,11 @@ define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ult_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpnlesd %xmm0, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm2, %xmm0
; SSE-NEXT: andnpd %xmm3, %xmm1
-; SSE-NEXT: orpd %xmm2, %xmm1
-; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: orpd %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ult_f64:
@@ -538,9 +558,10 @@ define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_ule_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpnltss %xmm0, %xmm1
-; SSE-NEXT: andps %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: andnps %xmm3, %xmm1
-; SSE-NEXT: orps %xmm2, %xmm1
+; SSE-NEXT: orps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -565,10 +586,11 @@ define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_ule_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpnltsd %xmm0, %xmm1
-; SSE-NEXT: andpd %xmm1, %xmm2
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: andpd %xmm2, %xmm0
; SSE-NEXT: andnpd %xmm3, %xmm1
-; SSE-NEXT: orpd %xmm2, %xmm1
-; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: orpd %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_ule_f64:
@@ -592,9 +614,10 @@ define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) {
; SSE-LABEL: select_fcmp_une_f32:
; SSE: # %bb.0:
; SSE-NEXT: cmpneqss %xmm1, %xmm0
-; SSE-NEXT: andps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andnps %xmm3, %xmm0
-; SSE-NEXT: orps %xmm2, %xmm0
+; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_une_f32:
@@ -618,9 +641,10 @@ define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) {
; SSE-LABEL: select_fcmp_une_f64:
; SSE: # %bb.0:
; SSE-NEXT: cmpneqsd %xmm1, %xmm0
-; SSE-NEXT: andpd %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: andpd %xmm2, %xmm1
; SSE-NEXT: andnpd %xmm3, %xmm0
-; SSE-NEXT: orpd %xmm2, %xmm0
+; SSE-NEXT: orpd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: select_fcmp_une_f64:
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll b/llvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll
index 22ba8fab86a..c2228046d60 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll
@@ -4,7 +4,7 @@ define i32 @f20u(double %x) #0 {
; CHECK-LABEL: name: f20u
; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:fr64 = COPY $xmm0
-; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = fpexcept CVTTSD2SI64rr [[COPY]], implicit $mxcsr
+; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY]], implicit $mxcsr
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[CVTTSD2SI64rr]].sub_32bit
; CHECK: $eax = COPY [[COPY1]]
; CHECK: RET 0, $eax
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
index 8fc496a05f1..75f5c0b93c7 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
@@ -6,7 +6,7 @@ entry:
; CHECK: [[MOVSX32rm8_:%[0-9]+]]:gr32 = MOVSX32rm8 %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 1 from %fixed-stack.0, align 16)
; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr killed [[MOVSX32rm8_]]
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[CVTSI2SDrr]] :: (store 8 into %stack.0, align 4)
-; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
+; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = nofpexcept LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
; CHECK: RET 0, killed [[LD_Fp64m80_]]
%result = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %result
@@ -18,7 +18,7 @@ entry:
; CHECK: [[MOVSX32rm16_:%[0-9]+]]:gr32 = MOVSX32rm16 %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 2 from %fixed-stack.0, align 16)
; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr killed [[MOVSX32rm16_]]
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[CVTSI2SDrr]] :: (store 8 into %stack.0, align 4)
-; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
+; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = nofpexcept LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
; CHECK: RET 0, killed [[LD_Fp64m80_]]
%result = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %result
@@ -29,14 +29,14 @@ entry:
; CHECK-LABEL: name: f20u64
; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
-; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
+; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
; CHECK: JCC_1
; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
-; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
+; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[SUBSDrr]] :: (store 8 into %stack.0)
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
-; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = fpexcept LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
+; CHECK: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0)
; CHECK: FNSTCW16m %stack.1, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (store 2 into %stack.1)
; CHECK: [[MOVZX32rm16_:%[0-9]+]]:gr32 = MOVZX32rm16 %stack.1, 1, $noreg, 0, $noreg :: (load 2 from %stack.1)
; CHECK: [[OR32ri:%[0-9]+]]:gr32 = OR32ri killed [[MOVZX32rm16_]], 3072, implicit-def $eflags
@@ -59,7 +59,7 @@ entry:
define i8 @f20s8(double %x) #0 {
entry:
; CHECK-LABEL: name: f20s8
-; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
+; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY [[CVTTSD2SIrm]]
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: $al = COPY [[COPY1]]
@@ -71,7 +71,7 @@ entry:
define i16 @f20s16(double %x) #0 {
entry:
; CHECK-LABEL: name: f20s16
-; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
+; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.0, align 16)
; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrm]].sub_16bit
; CHECK: $ax = COPY [[COPY]]
; CHECK: RET 0, $ax
@@ -84,15 +84,15 @@ entry:
; CHECK-LABEL: name: f20u
; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.0, align 16)
; CHECK: [[MOVSDrm_alt1:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
-; CHECK: fpexcept COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
+; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
; CHECK: [[FsFLD0SD:%[0-9]+]]:fr64 = FsFLD0SD
; CHECK: JCC_1
; CHECK: [[PHI:%[0-9]+]]:fr64 = PHI [[MOVSDrm_alt1]], {{.*}}, [[FsFLD0SD]], {{.*}}
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
; CHECK: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[MOVZX32rr8_]], 31, implicit-def dead $eflags
-; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = fpexcept SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
-; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = fpexcept CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
+; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
+; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
; CHECK: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[CVTTSD2SIrr]], killed [[SHL32ri]], implicit-def dead $eflags
; CHECK: $eax = COPY [[XOR32rr]]
; CHECK: RET 0, $eax
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
index 6870792321f..6abf34c6041 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -7,18 +7,18 @@ define float @foo(float %f) #0 {
; CHECK: body:
; CHECK: %0:fr32 = COPY $xmm0
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
-; CHECK: %3:fr32 = VMULSSrr %0, %1
+; CHECK: %3:fr32 = nofpexcept VMULSSrr %0, %1
; CHECK: %4:fr32 = VMOVSSrm
-; CHECK: %5:fr32 = VFMADD213SSr %1, killed %3, %4
+; CHECK: %5:fr32 = nofpexcept VFMADD213SSr %1, killed %3, %4
; CHECK: %6:fr32 = VMOVSSrm
-; CHECK: %7:fr32 = VMULSSrr %1, %6
-; CHECK: %8:fr32 = VMULSSrr killed %7, killed %5
-; CHECK: %9:fr32 = VMULSSrr %0, %8
-; CHECK: %10:fr32 = VFMADD213SSr %8, %9, %4
-; CHECK: %11:fr32 = VMULSSrr %9, %6
-; CHECK: %12:fr32 = VMULSSrr killed %11, killed %10
+; CHECK: %7:fr32 = nofpexcept VMULSSrr %1, %6
+; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5
+; CHECK: %9:fr32 = nofpexcept VMULSSrr %0, %8
+; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, %4
+; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, %6
+; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10
; CHECK: %14:fr32 = FsFLD0SS
-; CHECK: %15:fr32 = VCMPSSrr %0, killed %14, 0
+; CHECK: %15:fr32 = nofpexcept VCMPSSrr %0, killed %14, 0
; CHECK: %17:vr128 = VPANDNrr killed %16, killed %13
; CHECK: $xmm0 = COPY %18
; CHECK: RET 0, $xmm0
@@ -31,16 +31,16 @@ define float @rfoo(float %f) #0 {
; CHECK: body: |
; CHECK: %0:fr32 = COPY $xmm0
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
-; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %1
+; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %1
; CHECK: %4:fr32 = VMOVSSrm
-; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %1, killed %3, %4
+; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %1, killed %3, %4
; CHECK: %6:fr32 = VMOVSSrm
-; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %1, %6
-; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %7, killed %5
-; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %8
-; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %8, killed %9, %4
-; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %8, %6
-; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %11, killed %10
+; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %1, %6
+; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5
+; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %8
+; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, %4
+; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, %6
+; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10
; CHECK: $xmm0 = COPY %12
; CHECK: RET 0, $xmm0
%sqrt = tail call float @llvm.sqrt.f32(float %f)
diff --git a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
index a8d1b53c37c..6b9d84be407 100644
--- a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
+++ b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
@@ -3,7 +3,7 @@
define <1 x float> @constrained_vector_fadd_v1f32() #0 {
; CHECK-LABEL: name: constrained_vector_fadd_v1f32
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
-; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
+; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
; CHECK: $xmm0 = COPY [[ADDSSrm]]
; CHECK: RET 0, $xmm0
entry:
@@ -15,9 +15,9 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 {
; CHECK-LABEL: name: constrained_vector_fadd_v3f32
; CHECK: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
; CHECK: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
-; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = fpexcept ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
-; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
-; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = fpexcept ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
+; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
+; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
+; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY [[ADDSSrm1]]
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[ADDSSrm]]
; CHECK: [[UNPCKLPSrr:%[0-9]+]]:vr128 = UNPCKLPSrr [[COPY1]], killed [[COPY]]
@@ -38,8 +38,8 @@ entry:
define <4 x double> @constrained_vector_fadd_v4f64() #0 {
; CHECK-LABEL: name: constrained_vector_fadd_v4f64
; CHECK: [[MOVAPDrm:%[0-9]+]]:vr128 = MOVAPDrm $rip, 1, $noreg, %const.0, $noreg :: (load 16 from constant-pool)
-; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
-; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
+; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
+; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
; CHECK: $xmm0 = COPY [[ADDPDrm]]
; CHECK: $xmm1 = COPY [[ADDPDrm1]]
; CHECK: RET 0, $xmm0, $xmm1
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