diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll | 15 |
2 files changed, 21 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 18e567fa589..cea59de3e8a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11882,6 +11882,12 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N, SDLoc dl(N); SDValue Op(N, 0); + // Don't handle ppc_fp128 here or i1 conversions. + if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) + return SDValue(); + if (Op.getOperand(0).getValueType() == MVT::i1) + return SDValue(); + SDValue FirstOperand(Op.getOperand(0)); bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD && (FirstOperand.getValueType() == MVT::i8 || @@ -11910,11 +11916,6 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N, return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld); } - // Don't handle ppc_fp128 here or i1 conversions. - if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) - return SDValue(); - if (Op.getOperand(0).getValueType() == MVT::i1) - return SDValue(); // For i32 intermediate values, unfortunately, the conversion functions // leave the upper 32 bits of the value are undefined. Within the set of diff --git a/llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll b/llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll new file mode 100644 index 00000000000..ad8dd90ea92 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll @@ -0,0 +1,15 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr9 \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; Ensure we don't crash by trying to convert directly from a subword load +; to a ppc_fp128 as we do for conversions to f32/f64. +define ppc_fp128 @test(i16* nocapture readonly %Ptr) { +entry: + %0 = load i16, i16* %Ptr, align 2 + %conv = uitofp i16 %0 to ppc_fp128 + ret ppc_fp128 %conv +; CHECK: lhz [[LD:[0-9]+]], 0(3) +; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]] +; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]] +; CHECK: bl __gcc_qadd +} |
