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-rw-r--r--llvm/lib/Target/CellSPU/SPUISelLowering.cpp2
-rw-r--r--llvm/test/CodeGen/CellSPU/div_ops.ll22
2 files changed, 22 insertions, 2 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 014fbbedb70..0fa511eade3 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -97,8 +97,6 @@ namespace {
SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileELF()),
SPUTM(TM) {
- // Fold away setcc operations if possible.
- setPow2DivIsCheap();
// Use _setjmp/_longjmp instead of setjmp/longjmp.
setUseUnderscoreSetJmp(true);
diff --git a/llvm/test/CodeGen/CellSPU/div_ops.ll b/llvm/test/CodeGen/CellSPU/div_ops.ll
new file mode 100644
index 00000000000..0c93d83ca76
--- /dev/null
+++ b/llvm/test/CodeGen/CellSPU/div_ops.ll
@@ -0,0 +1,22 @@
+; RUN: llc --march=cellspu %s -o - | FileCheck %s
+
+; signed division rounds towards zero, rotma don't.
+define i32 @sdivide (i32 %val )
+{
+; CHECK: rotmai
+; CHECK: rotmi
+; CHECK: a
+; CHECK: rotmai
+; CHECK: bi $lr
+ %rv = sdiv i32 %val, 4
+ ret i32 %rv
+}
+
+define i32 @udivide (i32 %val )
+{
+; CHECK: rotmi
+; CHECK: bi $lr
+ %rv = udiv i32 %val, 4
+ ret i32 %rv
+}
+
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