diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse41-blend.ll | 17 | 
3 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index de3a568dd1e..508ab2163eb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -64,6 +64,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {                           Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;    case ISD::LOAD:        Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;    case ISD::SELECT:      Res = PromoteIntRes_SELECT(N); break; +  case ISD::VSELECT:     Res = PromoteIntRes_VSELECT(N); break;    case ISD::SELECT_CC:   Res = PromoteIntRes_SELECT_CC(N); break;    case ISD::SETCC:       Res = PromoteIntRes_SETCC(N); break;    case ISD::SHL:         Res = PromoteIntRes_SHL(N); break; @@ -465,6 +466,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {                       LHS.getValueType(), N->getOperand(0),LHS,RHS);  } +SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) { +  SDValue Mask = GetPromotedInteger(N->getOperand(0)); +  SDValue LHS = GetPromotedInteger(N->getOperand(1)); +  SDValue RHS = GetPromotedInteger(N->getOperand(2)); +  return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), +                     LHS.getValueType(), Mask, LHS, RHS); +} +  SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {    SDValue LHS = GetPromotedInteger(N->getOperand(2));    SDValue RHS = GetPromotedInteger(N->getOperand(3)); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index a9523f52861..0b8f911fbb1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -240,6 +240,7 @@ private:    SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);    SDValue PromoteIntRes_SDIV(SDNode *N);    SDValue PromoteIntRes_SELECT(SDNode *N); +  SDValue PromoteIntRes_VSELECT(SDNode *N);    SDValue PromoteIntRes_SELECT_CC(SDNode *N);    SDValue PromoteIntRes_SETCC(SDNode *N);    SDValue PromoteIntRes_SHL(SDNode *N); diff --git a/llvm/test/CodeGen/X86/sse41-blend.ll b/llvm/test/CodeGen/X86/sse41-blend.ll index 5a169dc5e94..a21416b7a8a 100644 --- a/llvm/test/CodeGen/X86/sse41-blend.ll +++ b/llvm/test/CodeGen/X86/sse41-blend.ll @@ -9,6 +9,23 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {  } +;CHECK: vsel_4xi8 +;CHECK: blendvps +;CHECK: ret +define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { +  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2 +  ret <4 x i8> %vsel +} + +;CHECK: vsel_4xi16 +;CHECK: blendvps +;CHECK: ret +define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { +  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %v1, <4 x i16> %v2 +  ret <4 x i16> %vsel +} + +  ;CHECK: vsel_i32  ;CHECK: blendvps  ;CHECK: ret  | 

