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-rw-r--r--llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td6
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td66
-rw-r--r--llvm/test/MC/AArch64/SVE/sdot-diagnostics.s58
-rw-r--r--llvm/test/MC/AArch64/SVE/sdot.s32
-rw-r--r--llvm/test/MC/AArch64/SVE/udot-diagnostics.s58
-rw-r--r--llvm/test/MC/AArch64/SVE/udot.s32
6 files changed, 252 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index b37c6967727..94f0be01b3c 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -72,6 +72,12 @@ let Predicates = [HasSVE] in {
defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">;
defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">;
+ defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot">;
+ defm UDOT_ZZZ : sve_intx_dot<0b1, "udot">;
+
+ defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot">;
+ defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot">;
+
defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">;
defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">;
defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c759950daa7..4bcde3edbcf 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1458,6 +1458,72 @@ multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> {
}
//===----------------------------------------------------------------------===//
+// SVE Integer Dot Product Group
+//===----------------------------------------------------------------------===//
+
+class sve_intx_dot<bit sz, bit U, string asm, ZPRRegOp zprty1,
+ ZPRRegOp zprty2>
+: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm,
+ "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
+ bits<5> Zda;
+ bits<5> Zn;
+ bits<5> Zm;
+ let Inst{31-23} = 0b010001001;
+ let Inst{22} = sz;
+ let Inst{21} = 0;
+ let Inst{20-16} = Zm;
+ let Inst{15-11} = 0;
+ let Inst{10} = U;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zda;
+
+ let Constraints = "$Zda = $_Zda";
+}
+
+multiclass sve_intx_dot<bit opc, string asm> {
+ def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>;
+ def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE Integer Dot Product Group - Indexed Group
+//===----------------------------------------------------------------------===//
+
+class sve_intx_dot_by_indexed_elem<bit sz, bit U, string asm,
+ ZPRRegOp zprty1, ZPRRegOp zprty2,
+ ZPRRegOp zprty3, Operand itype>
+: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
+ asm, "\t$Zda, $Zn, $Zm$iop",
+ "", []>, Sched<[]> {
+ bits<5> Zda;
+ bits<5> Zn;
+ let Inst{31-23} = 0b010001001;
+ let Inst{22} = sz;
+ let Inst{21} = 0b1;
+ let Inst{15-11} = 0;
+ let Inst{10} = U;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zda;
+
+ let Constraints = "$Zda = $_Zda";
+}
+
+multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> {
+ def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
+ bits<2> iop;
+ bits<3> Zm;
+ let Inst{20-19} = iop;
+ let Inst{18-16} = Zm;
+ }
+ def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
+ bits<1> iop;
+ bits<4> Zm;
+ let Inst{20} = iop;
+ let Inst{19-16} = Zm;
+ }
+}
+
+//===----------------------------------------------------------------------===//
// SVE Integer Arithmetic - Unary Predicated Group
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s b/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s
new file mode 100644
index 00000000000..cc22f21aa24
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s
@@ -0,0 +1,58 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+sdot z0.s, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot z0.s, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.d, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot z0.d, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid restricted register for indexed vector.
+
+sdot z0.s, z1.b, z8.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sdot z0.s, z1.b, z8.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.d, z1.h, z16.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sdot z0.d, z1.h, z16.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+sdot z0.s, z1.b, z7.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot z0.s, z1.b, z7.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.s, z1.b, z7.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot z0.s, z1.b, z7.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.d, z1.h, z15.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: sdot z0.d, z1.h, z15.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot z0.d, z1.h, z15.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: sdot z0.d, z1.h, z15.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/sdot.s b/llvm/test/MC/AArch64/SVE/sdot.s
new file mode 100644
index 00000000000..dbc6b3eabc0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/sdot.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sdot z0.s, z1.b, z31.b
+// CHECK-INST: sdot z0.s, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x00,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 9f 44 <unknown>
+
+sdot z0.d, z1.h, z31.h
+// CHECK-INST: sdot z0.d, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x00,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 df 44 <unknown>
+
+sdot z0.s, z1.b, z7.b[3]
+// CHECK-INST: sdot z0.s, z1.b, z7.b[3]
+// CHECK-ENCODING: [0x20,0x00,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 bf 44 <unknown>
+
+sdot z0.d, z1.h, z15.h[1]
+// CHECK-INST: sdot z0.d, z1.h, z15.h[1]
+// CHECK-ENCODING: [0x20,0x00,0xff,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 ff 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/udot-diagnostics.s b/llvm/test/MC/AArch64/SVE/udot-diagnostics.s
new file mode 100644
index 00000000000..08abd77592e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/udot-diagnostics.s
@@ -0,0 +1,58 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+udot z0.s, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot z0.s, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.d, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot z0.d, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid restricted register for indexed vector.
+
+udot z0.s, z1.b, z8.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: udot z0.s, z1.b, z8.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.d, z1.h, z16.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: udot z0.d, z1.h, z16.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+udot z0.s, z1.b, z7.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot z0.s, z1.b, z7.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.s, z1.b, z7.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot z0.s, z1.b, z7.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.d, z1.h, z15.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: udot z0.d, z1.h, z15.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot z0.d, z1.h, z15.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: udot z0.d, z1.h, z15.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/udot.s b/llvm/test/MC/AArch64/SVE/udot.s
new file mode 100644
index 00000000000..0c3a392093c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/udot.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+udot z0.s, z1.b, z31.b
+// CHECK-INST: udot z0.s, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x04,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 9f 44 <unknown>
+
+udot z0.d, z1.h, z31.h
+// CHECK-INST: udot z0.d, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x04,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 df 44 <unknown>
+
+udot z0.s, z1.b, z7.b[3]
+// CHECK-INST: udot z0.s, z1.b, z7.b[3]
+// CHECK-ENCODING: [0x20,0x04,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 bf 44 <unknown>
+
+udot z0.d, z1.h, z15.h[1]
+// CHECK-INST: udot z0.d, z1.h, z15.h[1]
+// CHECK-ENCODING: [0x20,0x04,0xff,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 ff 44 <unknown>
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