diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 16 |
2 files changed, 12 insertions, 13 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index c4b42bd85c1..45bbcd88cbd 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -1173,14 +1173,9 @@ class T2JTI<dag oops, dag iops, InstrItinClass itin, : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; // Move to/from coprocessor instructions -class T1Cop<dag oops, dag iops, string asm, list<dag> pattern> +class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern> : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { - let Inst{31-28} = 0b1110; -} - -class T2Cop<dag oops, dag iops, string asm, list<dag> pattern> - : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { - let Inst{31-28} = 0b1111; + let Inst{31-28} = opc; } // Two-address instructions diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 83e0b1f61cd..34ab4538b7a 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3331,7 +3331,8 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */, class tMovRCopro<string opc, bit direction, dag oops, dag iops, list<dag> pattern> - : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), + : T2Cop<0b1110, oops, iops, + !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { let Inst{27-24} = 0b1110; let Inst{20} = direction; @@ -3369,7 +3370,8 @@ def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), class tMovRRCopro<string opc, bit direction, list<dag> pattern = [/* For disassembly only */]> - : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + : T2Cop<0b1110, (outs), + (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { let Inst{27-24} = 0b1100; let Inst{23-21} = 0b010; @@ -3395,7 +3397,8 @@ def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; class t2MovRCopro<string opc, bit direction, dag oops, dag iops, list<dag> pattern> - : T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), + : T2Cop<0b1111, oops, iops, + !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { let Inst{27-24} = 0b1110; let Inst{20} = direction; @@ -3431,7 +3434,8 @@ def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, class t2MovRRCopro<string opc, bit direction, list<dag> pattern = [/* For disassembly only */]> - : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + : T2Cop<0b1111, (outs), + (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { let Inst{27-24} = 0b1100; let Inst{23-21} = 0b010; @@ -3461,7 +3465,7 @@ def t2MRRC2 : t2MovRRCopro<"mrrc2", // Other Coprocessor Instructions. // -def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, +def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, @@ -3484,7 +3488,7 @@ def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, let Inst{23-20} = opc1; } -def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, +def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, |
