diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 45 |
2 files changed, 63 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 37fb50b13ff..0e6073a5c80 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -285,6 +285,24 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { &ARM::ValueMappings[ARM::SPR3OpsIdx]}); break; } + case G_FPEXT: { + LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); + LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); + if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32) + OperandsMapping = + getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], + &ARM::ValueMappings[ARM::SPR3OpsIdx]}); + break; + } + case G_FPTRUNC: { + LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); + LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); + if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64) + OperandsMapping = + getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], + &ARM::ValueMappings[ARM::DPR3OpsIdx]}); + break; + } case G_CONSTANT: case G_FRAME_INDEX: case G_GLOBAL_VALUE: diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 844bdf87da8..6273e7a72c3 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -65,6 +65,9 @@ define void @test_fma_s32() #2 { ret void } define void @test_fma_s64() #2 { ret void } + define void @test_fpext_s32_to_s64() #0 { ret void } + define void @test_fptrunc_s64_to_s32() #0 { ret void } + define void @test_soft_fp_s64() #0 { ret void } attributes #0 = { "target-features"="+vfp2"} @@ -1198,6 +1201,48 @@ body: | BX_RET 14, %noreg, implicit %d0 ... --- +name: test_fpext_s32_to_s64 +# CHECK-LABEL: name: test_fpext_s32_to_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %s0 + + %0(s32) = COPY %s0 + %1(s64) = G_FPEXT %0 + %d0 = COPY %1(s64) + BX_RET 14, %noreg, implicit %d0 +... +--- +name: test_fptrunc_s64_to_s32 +# CHECK-LABEL: name: test_fptrunc_s64_to_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %d0 + + %0(s64) = COPY %d0 + %1(s32) = G_FPTRUNC %0 + %s0 = COPY %1(s32) + BX_RET 14, %noreg, implicit %s0 +... +--- name: test_soft_fp_s64 # CHECK-LABEL: name: test_soft_fp_s64 legalized: true |
