diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse41-schedule.ll | 8 |
2 files changed, 4 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index ccdf23ff668..834a254f2cd 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1150,18 +1150,6 @@ def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>; def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rr")>; def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rm")>; -// BLENDVP S/D. -def ZnWriteFPU01Lat3 : SchedWriteRes<[ZnFPU013]> { - let Latency = 3; -} -def ZnWriteFPU01Lat3Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> { - let Latency = 11; - let NumMicroOps = 2; - let ResourceCycles = [1, 2]; -} -def : InstRW<[ZnWriteFPU01Lat3], (instregex "BLENDVP(S|D)rr0")>; -def : InstRW<[ZnWriteFPU01Lat3Ld, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>; - def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> { let NumMicroOps = 2; let Latency = 8; diff --git a/llvm/test/CodeGen/X86/sse41-schedule.ll b/llvm/test/CodeGen/X86/sse41-schedule.ll index 013eb8347b2..39052ba15fc 100644 --- a/llvm/test/CodeGen/X86/sse41-schedule.ll +++ b/llvm/test/CodeGen/X86/sse41-schedule.ll @@ -369,8 +369,8 @@ define <2 x double> @test_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x doub ; ZNVER1-SSE: # %bb.0: ; ZNVER1-SSE-NEXT: movapd %xmm0, %xmm3 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: movaps %xmm2, %xmm0 # sched: [1:0.25] -; ZNVER1-SSE-NEXT: blendvpd %xmm0, %xmm1, %xmm3 # sched: [3:0.33] -; ZNVER1-SSE-NEXT: blendvpd %xmm0, (%rdi), %xmm3 # sched: [11:0.67] +; ZNVER1-SSE-NEXT: blendvpd %xmm0, %xmm1, %xmm3 # sched: [1:0.50] +; ZNVER1-SSE-NEXT: blendvpd %xmm0, (%rdi), %xmm3 # sched: [8:0.50] ; ZNVER1-SSE-NEXT: movapd %xmm3, %xmm0 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: retq # sched: [1:0.50] ; @@ -499,8 +499,8 @@ define <4 x float> @test_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> ; ZNVER1-SSE: # %bb.0: ; ZNVER1-SSE-NEXT: movaps %xmm0, %xmm3 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: movaps %xmm2, %xmm0 # sched: [1:0.25] -; ZNVER1-SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3 # sched: [3:0.33] -; ZNVER1-SSE-NEXT: blendvps %xmm0, (%rdi), %xmm3 # sched: [11:0.67] +; ZNVER1-SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3 # sched: [1:0.50] +; ZNVER1-SSE-NEXT: blendvps %xmm0, (%rdi), %xmm3 # sched: [8:0.50] ; ZNVER1-SSE-NEXT: movaps %xmm3, %xmm0 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: retq # sched: [1:0.50] ; |
